Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

IEE Proceedings: Computers and Digital Techniques

Volumn 147, Issue 6, 2000, Pages 383-390

  Williams, A C ^a   Brown, A D ^a   Zwolinski, M ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ENERGY DISSIPATION; ENERGY UTILIZATION; OPTIMIZATION; SYSTEMS ANALYSIS;

DYNAMIC POWER; POWER ESTIMATION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0034313221     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20000807     Document Type: Article

References (32)

1. BAKER, K.R., CURRIE, A.J., and NICHOLS, K.G.: Multiple, objective optimisation in a behavioural synthesis system, IEE Proc. Circuits Devices Syst., 1993, 140, pp. 253-260
2. BAKER, K.R., BROWN, A.D., and CURRIE, A.J.: Optimisation efficiency in behavioural synthesis, IEE Proc. Circuits Devices Syst., 1994, 141, (5), pp. 399-406
3. BAKER, K.R.: Final Report: Application specific synthesis enforcing testability (ASSET). University of Southampton, October 1995
4. NIJHAR, T.P.K., and BROWN, A.D.: Source level optimisation of VHDL for behavioural synthesis, IEE Proc. Comput. Digit. Tech., 1997, 144, (1), pp. 1-6
5. NIJHAR, T.P.K., and BROWN, A.D.: HDL-specific source level behavioural optimisation, IEE Proc. Comput. Digit. Tech., 1997, 144, (2), pp. 138-144
6. BROWN, A.D., BAKER, K.R., and WILLIAMS, A.C.: Online testing of statically and dynamically scheduled synthesized systems, IEEE Trans. CAD, 1997, 16, (1), pp. 47-57
7. WILLIAMS, A.C.: A behavioural VHDL synthesis system using data path optimisation. PhD thesis, University of Southampton, UK, July 1997
8. WILLIAMS, A.C., BROWN, A.D., and BAIDAS, Z.A.: Hierarchical module expansion in a VHDL behavioural synthesis system. Forum on design languages 1998 (FDL98), 1998, Lausanne, Switzerland
9. WILLIAMS, A.C., BROWN, A.D., and ZWOLINSKI, M.: Inline test of synthesized systems exploiting latency analysis, IEE Proc. Comput. Digit. Tech., 147, (1), pp. 33-41
10. WILLIAMS, A.C., BROWN, A.D., and ZWOLINSKI, M.: A VHDL behavioural synthesis system featuring simultaneous optimisation of dynamic power, area and delay. Forum on design languages 2000 (FDL2000), Tubigen, Germany
11. BAIDAS, Z.A., BROWN, A.D., and WILLIAMS, A.C.: A VHDL behavioural synthesis system with floating point support. Forum on design laneuages 2000 (FDL2000), Tubigen, Germany
12. KIRKPATRICK, S., GELATT, C.D.Jr, and VECCHI, M.P.: Optimization by simulated annealing, Science, 1983, 220, (4598), pp. 671-680
13. SINGH, D., RABAEY, J.M., PEDRAM, M., CATTHOOR, F., RAJGOPAL, S., SEHGAL, N., and MOZDZEN, T.J.: Power conscious CAD tools and methodologies: A perspective, Five. IEEE, 83, (4), pp. 570-594
14. VEENDRICK, H.J.M.: Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE J. Solid-State Circuits, 1984, pp. 468-473
15. NAJIM, F.N.: A survey of power estimation techniques in VLSI circuits, IEEE Trans. VLSI., 1994, 2, (4), pp. 446-455
16. KANG, A.M.: Accurate simulation of power dissipation in VLSI circuits, IEEE J. Solid-State Circuits, 1986, SC-21, (5), pp. 889-891
17. VANOOSTENDE, P., SIX, P., and VENDEWALLE, J.: Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators, IEEE J. Solid-State Circuits, 1993, 28, (1), pp. 26-39
18. LANDMAN, P.E., and RABAEY, J.M.: Activity-sensitive architectural power analysis, IEEE Trans. CAD, 1996, 15, (6), pp. 571-587
19. BOGLIOLI, A., BENINI, L., and RICCO, B.: Power estimation of cell-based CMOS circuits. Design Automation Conference, 1996, Las Vegas, Nevada
20. MACII, E., PEDRAM, M., and SOMENZI, F.: High-level power modeling, estimation, and optimization. Design Automation Conference, 1997, Anaheim, California
21. RAGHUNATHAN, A., DEY, S., and JHA, N.K.: Register-transfer level estimation techniques for switching activity and power consumption. Proc. ICCAD, November 1996, San José, California, pp. 158-165
22. KHOURI, K.S., LAKSHMINARAYANA, G., and JHA, N.K.: Fast high-level power estimation for control-flow intensive designs. ISLPED98, Monterey, California
23. DEVADAS, S., and MALIK, S.: A survey of optimization techniques targeting low power VLSI circuits. 32nd ACM/IEEE Design Automation Conference, 1995, San Francisco, California
24. MUSOLL, E., and CORTADELLA, J.: High-level synthesis techniques for reducing the activity of functional units. ISLPD95
25. SAN MARTIN, R., and KNIGHT, J.P.: Optimizing power in ASIC behavioural synthesis, IEEE Design Test Comput., Summer, 1998, pp. 58-70
26. RAGHUNATHAN, A., and JHA, N.K.: Behavioral synthesis for low power. Proc. ICCD, 1994, San José, California
27. CHANDRAKASAN, A.P., POTKONJAK, M., MEHRA, R., RABAEY, J., and BRODERSEN, R.: Optimizing power using transformations, IEEE Trans. CAD, 1995, 14, (1), pp. 12-31
28. KUMAR, N., KATKOORI, S., RADER, L., and VEMURI, R.: Profile-driven behavioral synthesis for low-power VLSI systems, IEEE Design Test Comput., Fall, 1995, pp. 70-84
29. LAKSHMINARAYANA, G., and JHA, N.K.: High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors, IEEE Trans. CAD, 1999, 18, (3), pp. 265-281
30. LIU, D., and SVENSSON, C.: Trading speed for low power by choice of supply and threshold voltages, IEEE J. Solid-State Circuits, 1993, 28, (1), pp. 10-17
31. BENINI, L., and DE MICHELI, G.: Automatic synthesis of low-power gated clock finite-state machines, IEEE Trans. CAD, 1996, 15, (6), pp. 630-643
32. VEMURI, R., ROY, J., MAMTORA, P., and KUMAR, N.: Benchmarks for high level synthesis. Laboratory for Digital Design Environments, University of Cincinnati, 1991