In-line test of synthesised systems exploiting latency analysis

IEE Proceedings: Computers and Digital Techniques

Volumn 147, Issue 1, 2000, Pages 33-41

  Williams, A C ^a   Brown, A D ^a   Zwolinski, M ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; BUILT-IN SELF TEST; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; FAST FOURIER TRANSFORMS; ITERATIVE METHODS; MARKOV PROCESSES; MATRIX ALGEBRA; OPTIMIZATION; PROBABILITY; REDUCED INSTRUCTION SET COMPUTING;

IN-LINE TESTING; LATENCY ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0033889550     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20000161     Document Type: Article

References (22)

1. AITKEN, R.C.'An overview of test synthesis tools', IEEE, 1995, DTC-12, (2), pp. 8-15
2. CHICKERNAME, V, LEE, J.and PATEL, J.K.'Addressing design for testability at the architectural level', IEEE Trans.1994, CAD-13, (7), pp. 920-934
3. BHATTACHARYA, S.and DEY, S.'H-SCAN: a high level alternative to full scan testing with reduced area and test application overheads', 14th VLSI test symposium, 1996, pp. 74-80
4. ABRAMOV1CI, M.BREUER, M.A.and FRIEDMAN, A.D.'Digital systems testing and testable design, IEEE Press (1990)
5. AGRAWAL, V.D.KIME, C.R.and SALUJA, K.K.'A tutorial on builtin seiftest (I): Principles', IEEE, 1993, DTC-10, pp. 73-92
6. GIZOPOULOS, D.PASCHALIS, A.and ZORIAN, Y.'An effective BIST scheme for datapaths', IEEE international test conference, 1996, pp. 76-85
7. BROWN, A.D.BAKER, K.R.and WILLIAMS, A.C.'On-line testing of statically and dynamically scheduled synthesized systems', IEEE Trans.1997, CAD-16, (1), pp. 47-57
8. BAKER, K.R.CURRIE, A.J.and NICHOLS, K.G.'Multiple objective optimisation in a behavioural synthesis system', IEE Proc. G.1993, 140, (4), pp. 253-260
9. BAKER, K.R.BROWN, A.D.and CURRIE, A.J.'Optimisation efficiency in behavioural synthesis', IEE Pmc. G.I994, 141, (5), pp. 399(06
10. WILLIAMS, A.C.'A Behavioural VHDL synthesis system using data path optimisation'. 1997, PhD Thesis, University of Southampton
11. DEV, S.and POTKONJAK, M.'Nonscan design for testability techniques using RT-level desien information', IEEE Trans, 1997, CAD-16, (12), pp. 1488-1506
12. GHOSH, I.RAGHUNATHAN, A.and JHA, N.K.'Design for hierarchical testability of. RTL circuits obtained by behavioural synthesis', IEEE Trans, 1997,'CAD-16, (9), pp. 1001-1014
13. GHOSH, I.RAGHUNATHAN, A.and JHA, N.K.'A design for testability technique for RTL circuits using control/data flow extraction', IEEE Trans.1998, CAD-17, (8), pp. 706-723
14. CRAIG, G.L.KIME, C.R.and SALUJA, K.K.Test scheduling and control for VLSI built-in self-test', IEEE Trans.1988, C-37, (9), pp. 1099-1109 -v.
15. 'Trans test user guide, Version 1.0' (TransEDA Ltd, 1992)
16. 'IEEE standard VHDL reference manual'. IEEE Std 1076-1987, IEEE Catalogue No. SH11957, 1987
17. HARRISON, P.G.and PATEL, N.M.'Performance modelling of communication networks and computer architectures' (AddisonWesley, 1994), pp. 81-163
18. FREEDMAN, D.'Markov chains' (Springer-Verlag, 1983)
19. NAJIM, F.N.'Transition density: a new measure of activity in digital circuits', IEEE Trans.1993, CAD-12, (2), pp. 310-323
20. SINGH, D.RABAEY, J.A.PEDRAM, M.CATTHOOR, P.RAJGOPAL, S.SEHGAL, N.and MOZDZEN, T.J.'Power conscious CAD tools and methodoloaies: a perspective', Pmc. IEEE, 1995, 83, (4), pp. 570-594
21. Microelectronics Centre of North California: Hish-level synthesis workshop benchmarks, 1989, 1991
22. PANDA, PR.and DUTT, N.'I995 high level synthesis design repository, University of California, Irvine, technical report 95-04, 1995