Analytical delay model based on Boolean process

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 162-165

  Min, Yinghua ^a   Zhao, Zhuxing ^a   Li, Zhongcheng ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; CALCULATIONS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; FREQUENCIES; LOGIC GATES; MATHEMATICAL MODELS; POLYNOMIALS; SET THEORY; VECTORS;

ANALYTICAL DELAY MODEL; BOOLEAN PROCESS; FLOATING DELAY; SENSITIZATION; SPECIFIED TIME BETWEEN INPUT TRANSITIONS; TRANSITION DELAY; WAVEFORM POLYNOMIAL;

DELAY CIRCUITS;

EID: 0029698155     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)