Integrating variable-latency components into high-level synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 10, 2000, Pages 1105-1117

  Raghunathan, Vijay ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA FLOW ANALYSIS; DIGITAL ARITHMETIC; LOGIC CIRCUITS; LOGIC DESIGN; OPTIMIZATION; RESOURCE ALLOCATION;

HIGH LEVEL SYNTHESIS; REGISTER TRANSFER LEVEL; VARIABLE LATENCY COMPONENTS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034294476     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.875270     Document Type: Article

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