Architectural retiming: Pipelining latency-constrained circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 708-713

  Hassoun, Soha ^a   Ebeling, Carl ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CONSTRAINT THEORY; CRITICAL PATH ANALYSIS; DELAY CIRCUITS; LOGIC DESIGN; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; SHIFT REGISTERS;

ARCHITECTURAL RETIMING; LATENCY CONSTRAINED CIRCUITS;

TIMING CIRCUITS;

EID: 0029720742     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)