Effectiveness of microarchitecture test program generation

IEEE Design and Test of Computers

Volumn 17, Issue 4, 2000, Pages 38-49

  Utamaphethai, Noppanunt ^a   Blanton, R D Shawn ^a   Shen, John Paul ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

FINITE STATE MACHINE (FSM); MICROARCHITECTURE TESTING; REGISTERS;

MICROPROCESSOR CHIPS;

EID: 0034290773     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.895005     Document Type: Article

References (18)

1. R.E. Bryant. "Graph Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp. 677-691.
2. R.E. Bryant, D.L. Beatty, and C.J.H. Seger. "Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation," Proc. Design Automation Conference, June 1991, ACM, New York, NY, USA, pp. 397-402.
3. M.C. McFarland. "Formal Verification of Sequential Hardware: A Tutorial," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 5, May 1993, pp. 633-654.
4. K.L. McMillan, Symbolic Model Checking, Kluwer Academic Publishers, Boston, 1993.
5. M. Yoeli, "Formal Verification of Hardware Design," IEEE Computer Society Press, Los Alamitos, CA, 1990.
6. J.Burch and D.Dill. "Automatic Verification of Pipelined Microprocessor Control," Proc. Int'l Conf. on Computer Aided Verification, June 1994, Springer-Verlag, Berlin, Germany, pp. 68-80.
7. K.L. Nelson, A. Jain, and R.E. Bryant. "Formal Verification of a Superscalar Execution Unit," Proc. Design Automation Conference, ACM, New York, NY, USA, June 1997, pp. 161-166.
8. C.L. Berman and L.H. Trevillyan. "Functional Comparison of Logic Designs for VLSI Circuits," Proc. of Int'l Conf. on Computer Design, Nov. 1989, ACM, New York, NY, USA, USA, pp. 456-459
9. D.L. Beatty and R.E. Bryant. "Formally Verifying a Microprocessor Using a Simulation Methodology," Proc. of Design Automation Conf., June 1994, IEEE Computer Soc. Los Alamitos, CA, USA, pp. 596-602.
10. D. Geist et al, "Coverage-Directed Test Generation Using Symbolic Techniques," Proc. of the Int'l Conf. in Formal Methods in CAD, Nov. 1996, Springer-Verlag, Berlin, Germany, pp. 143-158.
11. R.C. Ho et al, "Architecture Validation for Processors," Proc. of the Int'l Symp. on Computer Architecture, June 1995, ACM, New York, NY, USA, pp. 404-413.
12. H. Iwashita et al. "Automatic Test Program Generation for Pipelined Processors," Proc. of Int'l Conf. on CAD, Nov. 1994, ACM, New York, NY, USA, pp. 580-583.
13. D. Moundanos, J.A. Abraham, and Y.V. Hoskote. "Abstraction Techniques for Validation Coverage Analysis and Test Generation," IEEE Trans. on Computers, Vol. 47, No. 1, Jan. 1998, pp. 2-14.
14. J. Shen and J.A. Abraham, "An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation," J. Electronic Testing (Theory and Applications), Vol. 16, No. 1-2, Feb. 2000, pp. 67-81.
15. C. Bechem et al. "A Functional Performance Simulator for Microarchitecture Evaluation and Validation," IEEE Micro, May-June 1999, pp. 26-35.
16. N. Utamaphethai, R. D. Blanton, and J. P. Shen, "A Buffer-Oriented Methodology for Microarchitecture Validation," J. Electronic Testing (Theory and Applications), Vol. 16, No. 1-2, Feb. 2000, pp. 49-65.
17. N. Utamaphethai, R. D. Blanton, and J. P. Shen. "Superscalar Processor Validation at the Microarchitecture Level," Proc. of Int'l Conf. on VLSI Design, Jan. 1999, , IEEE Computer Soc. Los Alamitos, CA, USA, pp. 300-305.
18. Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1978.