메뉴 건너뛰기




Volumn 33, Issue 12, 1986, Pages 1964-1970

An Accurate DC Model for High-Voltage Lateral DMOS Transistors Suited for CACD

Author keywords

[No Author keywords available]

Indexed keywords

TRANSISTORS, FIELD EFFECT - MATHEMATICAL MODELS;

EID: 0022880484     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1986.22854     Document Type: Article
Times cited : (15)

References (9)
  • 1
    • 84939331221 scopus 로고
    • An integrated 8-MHz video output amplifier
    • Aug.
    • P. G. Blanken and P. van der Zee, “An integrated 8-MHz video output amplifier,” IEEE Trans. Consumer Electron., vol. CE-31, no. 3, pp. 109–118, Aug. 1985.
    • (1985) IEEE Trans. Consumer Electron , vol.CE-31 , Issue.3 , pp. 109-118
    • Blanken, P.G.1    van der Zee, P.2
  • 2
    • 0018985713 scopus 로고
    • Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors
    • Feb.
    • S. C. Sun and J. D. Plummer, “Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, pp. 356–367, Feb. 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , Issue.2 , pp. 356-367
    • Sun, S.C.1    Plummer, J.D.2
  • 3
    • 0019703894 scopus 로고
    • Effects of drift region parameters on the static properties of power LDMOST
    • Dec.
    • S. Colak, “Effects of drift region parameters on the static properties of power LDMOST,” IEEE Trans. Electron Devices, vol. ED-28, no. 12, pp. 51–53, Dec. 1981.
    • (1981) IEEE Trans. Electron Devices , vol.ED-28 , Issue.12 , pp. 51-53
    • Colak, S.1
  • 4
    • 0017007713 scopus 로고
    • A computer-aided design model for high-voltage lateral Double Diffused MOS (DMOS) Transistors
    • Oct.
    • M. D. Pocha and R. W. Dutton, “A computer-aided design model for high-voltage lateral Double Diffused MOS (DMOS) Transistors,” IEEE J. Solid-State Circuits, vol. SC-11, no. 5, pp. 718–726, Oct. 1976.
    • (1976) IEEE J. Solid-State Circuits , vol.SC-11 , Issue.5 , pp. 718-726
    • Pocha, M.D.1    Dutton, R.W.2
  • 6
    • 0018995379 scopus 로고
    • Modeling of scaled-down transistors
    • F. M. Klaassen and W. C. J. de Groot, “Modeling of scaled-down transistors,” Solid-State Electron., vol. 23, pp. 237–242, 1980.
    • (1980) Solid-State Electron , vol.23 , pp. 237-242
    • Klaassen, F.M.1    de Groot, W.C.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.