메뉴 건너뛰기




Volumn 12, Issue 6, 1993, Pages 829-836

Intractability in Linear Switch-Level Simulation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; HEURISTIC METHODS; MATHEMATICAL MODELS; PIECEWISE LINEAR TECHNIQUES; TRANSISTORS;

EID: 0027608988     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.229758     Document Type: Article
Times cited : (3)

References (24)
  • 2
    • 0021377624 scopus 로고
    • A switch-level model and simulator for MOS digital systems
    • Feb.
    • R. E. Bryant, “A switch-level model and simulator for MOS digital systems,” IEEE Trans. Comput., vol. C-33, pp. 160–177, Feb. 1984.
    • (1984) IEEE Trans. Comput. , vol.C-33 , pp. 160-177
    • Bryant, R.E.1
  • 3
    • 0023383889 scopus 로고
    • Algorithmic aspects of symbolic switch network analysis
    • July
    • R. E. Bryant, “Algorithmic aspects of symbolic switch network analysis,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 618–633, July 1987.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , pp. 618-633
    • Bryant, R.E.1
  • 4
    • 0023383023 scopus 로고
    • Boolean analysis of MOS circuits
    • July
    • R. E. Bryant, “Boolean analysis of MOS circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 634–649, July 1987.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , pp. 634-649
    • Bryant, R.E.1
  • 8
    • 0000208736 scopus 로고
    • The generalized adjoint network and network sensitivities
    • Aug.
    • S. W. Director and R. A. Rohrer, “The generalized adjoint network and network sensitivities,” in IEEE Trans. circuit Theory, vol. 16, pp. 318–323, Aug. 1969.
    • (1969) IEEE Trans. circuit Theory , vol.16 , pp. 318-323
    • Director, S.W.1    Rohrer, R.A.2
  • 9
    • 84941436341 scopus 로고
    • Logic equations and switch level circuit simulation
    • (Advances in CAD for VLSI), A. E. Ruehli, ed. New York: North-Holland
    • G. S. Ditlow and A. E. Ruehli, “Logic equations and switch level circuit simulation,” in Circuit Analysis, Simulation and Design, Part 2 (Advances in CAD for VLSI, vol. 3), A. E. Ruehli, ed. New York: North-Holland, 1987.
    • (1987) Circuit Analysis, Simulation and Design, Part 2 , vol.3
    • Ditlow, G.S.1    Ruehli, A.E.2
  • 11
    • 84941431012 scopus 로고
    • Improved methods for modeling uncertainty in RC timing analysis
    • Nov.
    • C. L. Harkness and D. Lopresti, “Improved methods for modeling uncertainty in RC timing analysis,” Brown Univ., Tech. Rep. CS-89-43, Nov. 1989.
    • (1989) Brown Univ., Tech. Rep. CS-89-43
    • Harkness, C.L.1    Lopresti, D.2
  • 12
    • 0024890973 scopus 로고
    • Modeling uncertainty in RC timing analysis
    • Nov.
    • C. L. Harkness and D. Lopresti, “Modeling uncertainty in RC timing analysis,” in Proc. IEEE Int. Conf. CAD, pp. 516–519, Nov. 1989.
    • (1989) Proc. IEEE Int. Conf. CAD , pp. 516-519
    • Harkness, C.L.1    Lopresti, D.2
  • 13
    • 84941445419 scopus 로고
    • Simulating switch-level networks with uncertain transistor strengths and node sizes
    • Feb.
    • C. L. Harkness and D. Lopresti, “Simulating switch-level networks with uncertain transistor strengths and node sizes,” Brown Univ., Tech. Rep. CS-89-07, Feb. 1989.
    • (1989) Brown Univ., Tech. Rep. CS-89-07
    • Harkness, C.L.1    Lopresti, D.2
  • 16
    • 0004293209 scopus 로고
    • (Automatic Computation Series). Englewood Cliffs, NJ: Prentice-Hall
    • R. Moore, Interval Analysis (Automatic Computation Series). Englewood Cliffs, NJ: Prentice-Hall, 1966.
    • (1966) Interval Analysis
    • Moore, R.1
  • 17
    • 0020502658 scopus 로고
    • Crystal: A timing analyzer for nMOS VLSI circuits
    • Randal E. Bryant, ed
    • J. K. Ousterhout, “Crystal: A timing analyzer for nMOS VLSI circuits,” in Proc. Third Caltech Conf. VLSI, Randal E. Bryant, ed. pp. 57–70, 1983.
    • (1983) Proc. Third Caltech Conf. VLSI , pp. 57-70
    • Ousterhout, J.K.1
  • 18
    • 0021120602 scopus 로고
    • Switch-level delay models for digital MOS VLSI
    • June
    • J. K. Ousterhout, “Switch-level delay models for digital MOS VLSI,” in Proc. 1984 Design Automation Conf., pp. 542–548, June 1984.
    • (1984) Proc. 1984 Design Automation Conf , pp. 542-548
    • Ousterhout, J.K.1
  • 20
    • 0023867792 scopus 로고
    • Circuit partitioning simplified
    • Jan.
    • R. A. Rohrer, “Circuit partitioning simplified,” IEEE Trans. Circuits Syst., vol. 35, pp. 2–5, Jan. 1988.
    • (1988) IEEE Trans. Circuits Syst. , vol.35 , pp. 2-5
    • Rohrer, R.A.1
  • 23
    • 84941486964 scopus 로고
    • Piecewise linear analysis and simulation
    • Advances in CAD for VLSI A. E. Ruehli, ed. New York: North-Holland
    • W. M. G. van Bokhoven, “Piecewise linear analysis and simulation,” in Circuit Analysis, Simulation and Design, Part 2, (Advances in CAD for VLSI, vol. 3), A. E. Ruehli, ed. New York: North-Holland, 1987.
    • (1987) Circuit Analysis, Simulation and Design, Part 2 , vol.3
    • van Bokhoven, W.M.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.