-
1
-
-
84944982891
-
A survey of optimization techniques for integrated circuit design
-
Oct.
-
R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli, “A survey of optimization techniques for integrated circuit design,” Proc. IEEE, vol. 69, pp. 1334–1362, Oct. 1981.
-
(1981)
Proc. IEEE
, vol.69
, pp. 1334-1362
-
-
Brayton, R.K.1
Hachtel, G.D.2
Sangiovanni-Vincentelli, A.L.3
-
2
-
-
0022603501
-
A methodology for worst-case analysis of integrated circuits
-
Jan.
-
S. R. Nassif, A. J. Strojwas, and S. W. Director, “A methodology for worst-case analysis of integrated circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, pp. 104–113, Jan. 1986.
-
(1986)
IEEE Trans. Computer-Aided Design
, vol.CAD-5
, Issue.1
, pp. 104-113
-
-
Nassif, S.R.1
Strojwas, A.J.2
Director, S.W.3
-
3
-
-
0003687677
-
-
New York: Wiley
-
G. E. P. Box, W. J. Hunter, and J. S. Hunter, Statistics for Experimenters: An Introduction to Design, Data Analysis, and Model Building. New York: Wiley, 1978.
-
(1978)
Statistics for Experimenters: An Introduction to Design, Data Analysis, and Model Building.
-
-
Box, G.E.P.1
Hunter, W.J.2
Hunter, J.S.3
-
5
-
-
25844521485
-
Statistical performance modeling and parametric yield estimation of MOS VLSI
-
Nov.
-
T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, “Statistical performance modeling and parametric yield estimation of MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1013–1022, Nov. 1987.
-
(1987)
IEEE Trans. Computer-Aided Design
, vol.CAD-6
, pp. 1013-1022
-
-
Yu, T.K.1
Kang, S.M.2
Hajj, I.N.3
Trick, T.N.4
-
7
-
-
0024931842
-
An efficient methodology for building macromodels of IC fabrication processes
-
Dec.
-
K. K. Low and S. W. Director, “An efficient methodology for building macromodels of IC fabrication processes,” IEEE Trans. Computer-Aided Design, vol. 8, no. 12, pp. 1299–1313, Dec. 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, Issue.12
, pp. 1299-1313
-
-
Low, K.K.1
Director, S.W.2
-
8
-
-
0026839811
-
Integrated circuit design optimization using a sequential strategy
-
March
-
M. C. Bernardo, R. Buck, L. Liu, W. A. Nazaret, J. Sacks, and W. J. Welch, “Integrated circuit design optimization using a sequential strategy,” IEEE Trans. Computer-Aided Design, vol. 11, no. 3, pp. 361–372, March 1992.
-
(1992)
IEEE Trans. Computer-Aided Design
, vol.11
, Issue.3
, pp. 361-372
-
-
Bernardo, M.C.1
Buck, R.2
Liu, L.3
Nazaret, W.A.4
Sacks, J.5
Welch, W.J.6
-
9
-
-
0018468345
-
A comparison of three methods for selecting values of input variables in the analysis of output from a computer code
-
May
-
M. D. McKay, R. J. Beckman, and W. J. Conover, “A comparison of three methods for selecting values of input variables in the analysis of output from a computer code,” Technometrics, vol. 21, no. 2, pp. 239–245, May 1979.
-
(1979)
Technometrics
, vol.21
, Issue.2
, pp. 239-245
-
-
McKay, M.D.1
Beckman, R.J.2
Conover, W.J.3
-
10
-
-
0022594787
-
Statistical circuit design with a dynamic constraint approximation scheme
-
R. M. Biernacki and M. A. Styblinski, “Statistical circuit design with a dynamic constraint approximation scheme,” in Proc. IEEE Int. Symp. Circuits Syst., 1986, pp. 976–979.
-
(1986)
Proc. IEEE Int. Symp. Circuits Syst.
, pp. 976-979
-
-
Biernacki, R.M.1
Styblinski, M.A.2
-
11
-
-
0023434904
-
Realistic worst-case parameters for circuit simulation
-
Oct.
-
P. Tuohy, A. Gribben, A. J. Walton, and J. M. Robertson, “Realistic worst-case parameters for circuit simulation,” IEE Proc., vol. 134, no. 5, pp. 137–140, Oct. 1987.
-
(1987)
IEE Proc.
, vol.134
, Issue.5
, pp. 137-140
-
-
Tuohy, P.1
Gribben, A.2
Walton, A.J.3
Robertson, J.M.4
-
12
-
-
0025590486
-
Limit-parameters: the general solution of the worst-case problem for the linearized case
-
G. E. Müller-L., “Limit-parameters: the general solution of the worst-case problem for the linearized case,” in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 2256–2259.
-
(1990)
Proc. IEEE Int. Symp. Circuits Syst.
, pp. 2256-2259
-
-
Müller, G.E.-L.1
-
14
-
-
0003468941
-
-
Department of Operations Research, Stanford Univ., Stanford, CA, Rep. SOL86-2
-
P. E. Gill, W. Murray, M. A. Saunders, and M. H. Wright, “User's guide for NPSOL, version 4.0,” Department of Operations Research, Stanford Univ., Stanford, CA, Rep. SOL86-2, 1986.
-
(1986)
User's guide for NPSOL, version 4.0
-
-
Gill, P.E.1
Murray, W.2
Saunders, M.A.3
Wright, M.H.4
-
15
-
-
0022752950
-
Modification of the Banu-Tsividis continuous-time integrator structure
-
July
-
Z. Czamul, “Modification of the Banu-Tsividis continuous-time integrator structure,” IEEE Trans. Circuits Syst., vol. CAS-33, pp. 714–716, July 1986.
-
(1986)
IEEE Trans. Circuits Syst.
, vol.CAS-33
, pp. 714-716
-
-
Czamul, Z.1
-
16
-
-
0027664687
-
ILLIADS: a fast timing and reliability simulator for digital MOS circuits
-
Sept.
-
Y. H. Shih, Y. Leblebici and S. M. Kang, “ILLIADS: a fast timing and reliability simulator for digital MOS circuits,” IEEE Trans. Computer-Aided Design, vol. 12, no. 9, pp. 1387–1402, Sept. 1993.
-
(1993)
IEEE Trans. Computer-Aided Design
, vol.12
, Issue.9
, pp. 1387-1402
-
-
Shih, Y.H.1
Leblebici, Y.2
Kang, S.M.3
-
17
-
-
0023994941
-
DELIGHT.SPICE: an optimization-based system for the design of integrated circuits
-
April
-
W. Nye, D.C. Riley, A. L. Sangiovanni-Vincentelli, and A. L. Tits, “DELIGHT.SPICE: an optimization-based system for the design of integrated circuits,” IEEE Trans. Computer-Aided Design, vol. 7, no. 4, pp. 501–519, April 1988.
-
(1988)
IEEE Trans. Computer-Aided Design
, vol.7
, Issue.4
, pp. 501-519
-
-
Nye, W.1
Riley, D.C.2
Sangiovanni-Vincentelli, A.L.3
Tits, A.L.4
-
18
-
-
0026186319
-
A new methodology for the design centering of IC fabrication processes
-
July
-
K. K. Low and S. W. Director, “A new methodology for the design centering of IC fabrication processes,” IEEE Trans. Computer-Aided Design, vol. 10, no. 7, pp. 895–903, July 1991.
-
(1991)
IEEE Trans. Computer-Aided Design
, vol.10
, Issue.7
, pp. 895-903
-
-
Low, K.K.1
Director, S.W.2
-
19
-
-
0000238336
-
A simplex method for function mimization
-
J. A. Nelder and R. Mead, “A simplex method for function mimization,” Comput. J., vol. 7, pp. 308–313, 1965.
-
(1965)
Comput. J.
, vol.7
, pp. 308-313
-
-
Nelder, J.A.1
Mead, R.2
-
20
-
-
0026991450
-
An integrated approach to realistic worst-case design optimization of MOS analog circuits
-
A. Dharchoudhury and S. M. Kang, “An integrated approach to realistic worst-case design optimization of MOS analog circuits,” in Proc. 29th ACM/IEEE Design Automation Conf., 1992, pp. 704–709.
-
(1992)
Proc. 29th ACM/IEEE Design Automation Conf.
, pp. 704-709
-
-
Dharchoudhury, A.1
Kang, S.M.2
-
22
-
-
0342384724
-
Theory of generalized least pth approximation
-
May
-
J. W. Bandler and C. Charalambous, “Theory of generalized least pth approximation,” IEEE Trans. Circuit Theory, vol. CT-19, pp. 287–289, May 1972.
-
(1972)
IEEE Trans. Circuit Theory
, vol.CT-19
, pp. 287-289
-
-
Bandler, J.W.1
Charalambous, C.2
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