Global optimization for digital MOS circuits performance

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 1, 2000, Pages 161-164

  Chen, H M ^a   Samudra, G S ^a   Chan, D S H ^a   Ibrahim, Yaacob ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; GENETIC ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; OPTIMIZATION;

GLOBAL APPROXIMATION; PARAMETRIC YIELD; PERFORMANCE SPREAD;

DIGITAL INTEGRATED CIRCUITS;

EID: 0033903697     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.822628     Document Type: Article

References (18)

1. R. Spence and R. S. Soin, Tolérance Design of Electronic Circuits. Workingham, U.K.: Addison Wesley, 1988.
2. D. E. Hocevar, P. F. Cox, and P. Yang, "Parametric yield optimization for MOS circuit blocks," IEEE Trans. Computer-Aided Design, vol. 7, June 1988.
3. M. Singha and R. Spence, "The parametric yield enhancement of integrated circuits," Int. J. Circuit Theory Applicat., vol. 19, pp. 565-578, 1991.
4. M. Conti, S. Orcioni, and C. Turchetii, "Parametric yield optimization of MOS VLSI circuits based on simulated annealing and its parallel implementation, " IEE Proc.Circuits Devices Syst., vol. 141, no. 5, Oct. 1994.
5. M. D. McKay, R. J. Beckman, and W. J. Conover, "A combination of three methods for selecting values of input variables in the analysis of output from a computer code," Technomet., vol. 21, no. 2, May 1979.
6. M. Keramat and R. Kielbasa, "Modified Latin Hypercube Sampling Monte Carlo (MLHSMC) estimation for average quality index," Analog Integr. Circuits Signal Processing, vol. 19, no. 1, pp. 87-98, Apr. 1999.
7. J. Chen and M. A. Styblinski, "A systematic approach of statistical modeling and its application to CMOS circuits," in Proc. IEEE Int. Symp. Circuits and Systems'93, Chicago, IL, May 1993, pp. 1805-1808.
8. M. A. Styblinski and S. Aftab, "Combination of interpolation and self-organizing approximation techniques-A new approach to circuit performance modeling," IEEE Trans. Computer-Aided Design, vol. 12, Nov. 1993.
9. J. C. Zhang and M. A. Styblinski, Yield and Variability Optimization of Integrated Circuits. Boston, MA: Kluwer Academic, 1995.
10. N. K. Raghu, "Off-line quality control, parameter design, and the Taguchi method," J. Quality Technoi, vol. 17, no. 4, Oct. 1985.
11. Z. Michalewicz, Genetic Algorithms + Data Structures = Evolution Programs. New York: Springer-Verlag, 1992.
12. Y. Shen and R. M. M. Chen, "Application of genetic algorithm for response surface modeling in optimal statistical design," in, 11995 IEEE Int. Symp. Circuits and Systems, vol. 3, 1995, pp. 2152-2155.
13. N. J. Elias, "Acceptance sampling: An efficient, accurate method for estimating and optimizing parametric yield," IEEE]. Solid-State Circuits, vol. 29, Mar. 1994.
14. S. W. Pan and Y. H. Hu, "PYFS-A statistical optimization method for integrated circuit yield enhancement," IEEE Trans. Computer-Aided Design, vol. 12, Feb. 1993.
15. M. D. MeehanandJ. Purviance, Yield and Reliability in Microwave Circuit and System Design. Boston, MA: Artech House, 1993.
16. M. C. Bernardo, R. Buck, and L. Liu, "Integrated Circuit Design Optimization Using a Sequential Strategy," IEEE Trans. Computer-Aided Design, vol. 11, Mar. 1992.
17. R. X. Gu, K. M. Sharaf, and M. I. Elmasry, High-Performance Digital VLSI Circuit Design. Boston, MA: Kluwer Academic, 1996.
18. L. Ingber and B. E. Rosen, "Genetic algorithms and very fast simulated reannealing," Math. Comput. Model., vol. 16, no. 11, pp. 87-100, 1992.