Parametric yield optimization of MOS VLSI circuits based on simulated annealing and its parallel implementation

IEE Proceedings: Circuits, Devices and Systems

Volumn 141, Issue 5, 1994, Pages 387-398

  Conti, M ^a   Orcioni, S ^a   Turchetti, C ^a  

^a UNIVERSITÀ POLITECNICA DELLE MARCHE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG COMPUTERS; COMPUTATIONAL METHODS; DIGITAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

GRADIENT ALGORITHM; PARAMETRIC YIELD OPTIMIZATION; SIMULATED ANNEALING ALGORITHM;

VLSI CIRCUITS;

EID: 0028525886     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19941202     Document Type: Article

References (12)