SCOPUS 정보 검색 플랫폼

Volumn 19, Issue 6, 1991, Pages 565-578

The Parametric Yield Enhancement of Integrated Circuits

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS, OPERATIONAL; COMPUTER PROGRAMMING--ALGORITHMS; ELECTRIC NETWORKS--TOPOLOGY;

MASS-PRODUCED CIRCUITS; PARAMETRIC YIELD ENHANCEMENT; TWO-STAGE OP AMP;

INTEGRATED CIRCUITS, CMOS;

EID: 0026256670 PISSN: 00989886 EISSN: 1097007X Source Type: Journal
DOI: 10.1002/cta.4490190605 Document Type: Article

Times cited : (9)

References (16)

2
- 0017515253
- The simplicial approximation approach to design centering
- (1977) IEEE Trans. Circuits and Systems , vol.24 CAS , pp. 363-372
- Director, S.W.¹ Hachtel, G.D.²

3
- 0020087855
- Design centering by yield prediction
- (1982) IEEE Trans. Circuits and Systems , vol.29 CAS , pp. 88-96
- Antreich, K.J.¹ Koblitz, R.K.²

4
- 0019592219
- Statistical design centering and tolerancing using parametric sampling
- (1981) IEEE Trans. Circuits and Systems , vol.28 CAS , pp. 692-702
- Singhal, K.¹ Pinel, J.F.²

5
- 84984357476
- New simple heuristic algorithms for yield maximisation', Proc. 1987, IEEE, New York
- (1988) IEEE Int. Symp. on Circuits and Systems , pp. 816-819
- Wehrhahn, E.¹

6
- 0019246429
- Statistical exploration approach to design centering
- pt. G
- (1980) Proc. IEE , vol.127 , pp. 260-269
- Soin, R.S.¹ Spence, R.²

7
- 0021627403
- The performance of some design centering methods
- IEEE, New York
- (1985) Proc. IEEE 1984 Int. Symp. on Circuits and Systems , pp. 1424-1438
- Wehrhahn, E.¹ Spence, R.²

8
- 0021202647
- Fabrics‐II: a statistically based IC fabrication process simulator
- (1984) IEEE Trans. Computer‐aided Design , vol.3 CAD , pp. 20-46
- Nassif, S.R.¹ Strojwas, A.J.² Director, S.W.³

9
- 0024934572
- IEEE 1989 Int. Conf. on Computer‐aided Design, IEEE, New York
- (1990) A new methodology for the design centering of IC fabrication processes , pp. 194-197
- Low, K.K.¹ Director, S.W.²

10
- 84984337862
- Tolerance design of analogue integrated circuits', ASCOT Project Report, Imperial College, December
- (1989)
- Singha, M.¹ Spence, R.²

11
- 84984360497
- The automated improvement of analogue integrated circuits', IEE Colloq. Digest 1990/107, June
- (1990)
- Singha, M.¹ Xiao, X‐M.² Spence, R.³

12
- 0022562544
- An integrated and efficient approach for MOS VLSI statistical circuit design
- (1986) IEEE Trans. Computer‐aided Design , vol.5 CAD , pp. 5-14
- Yang, P.¹ Hocevar, D.E.² Cox, P.F.³ Machala, C.⁴ Chatterjee, P.J.⁵

13
- 84984277494
- Rapid yield estimation as a computer aid for analog cell design', IEEE 1990 Custom Integrated Circuits Conf. IEEE, New York
- (1991) , pp. 5.1
- Mukherjee, T.¹ Carley, L.R.²

14
- 0024888770
- An efficient method for parametric yield optimisation of MOS integrated circuits
- IEEE, New York
- (1990) IEEE 1989 Int. Conf. on Computer‐aided Design , pp. 190-193
- Yu, T.K.¹ Kang, S.M.² Sacks, J.³ Welch, W.J.⁴

15
- 0025530930
- Computing parametric yield accurately and efficiently
- IEEE, New York
- (1991) IEEE 1990 Int. Conf. on Computer‐aided Design , pp. 116-119
- Milor, L.¹ Sangiovanni‐Vincentelli, A.²

16
- 84984301886
- CHIPAIDE: a new approach to analogue integrated circuit design', IEE Colloq. Digest 1990/073, May
- (1990)
- Makris, C.A.¹ Berrah, C.M.² Xiao, X.³ Singha, M.⁴ Illumoka, A.A.⁵ Stone, J.⁶ Toumazou, C.⁷ Cheung, P.Y.K.⁸ Spence, R.⁹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.