-
2
-
-
0037906016
-
New statistical methods for assigning device tolerances
-
Apr.
-
N. J. Elias, “New statistical methods for assigning device tolerances,” in Proc. IEEE Int. Symp. Circuits Syst., Apr. 1975, pp. 329-332.
-
(1975)
in Proc. IEEE Int. Symp. Circuits Syst.
, pp. 329-332
-
-
Elias, N.J.1
-
3
-
-
0017515253
-
The simplicial approximation approach to design centering
-
July
-
S. W. Director and G. D. Hachtel, “The simplicial approximation approach to design centering,” IEEE Trans. Circuits Syst., vol. CAS-24, no. 7, 363-372, July 1977.
-
(1977)
IEEE Trans. Circuits Syst.
, vol.CAS-24
, Issue.7
, pp. 363-372
-
-
Director, S.W.1
Hachtel, G.D.2
-
4
-
-
0018023947
-
Optimal centering, tolerancing, and yield determination via updated approximations and cuts
-
Oct.
-
J. W. Bandler and H. L. Abdel-Malek, “Optimal centering, tolerancing, and yield determination via updated approximations and cuts,” IEEE Trans. Circuits Syst., vol. CAS-25, no. 10, pp. 853-871, Oct. 1978.
-
(1978)
IEEE Trans. Circuits Syst.
, vol.CAS-25
, Issue.10
, pp. 853-871
-
-
Bandler, J.W.1
Abdel-Malek, H.L.2
-
5
-
-
0019246429
-
Statistical exploration approach to design centering
-
pt. G, Dec.
-
R. S. Soin and R. Spence, “Statistical exploration approach to design centering,” Proc. Inst. Elec. Eng., pt. G, vol. 127, no. 6, pp. 260-269, Dec. 1980.
-
(1980)
Proc. Inst. Elec. Eng.
, vol.127
, Issue.6
, pp. 260-269
-
-
Soin, R.S.1
Spence, R.2
-
6
-
-
0020778410
-
A study of variance reduction techniques for estimating circuit yield
-
July
-
D. E. Hocevar, M. R. Lightner, and T. N. Trick, “A study of variance reduction techniques for estimating circuit yield,” IEEE Trans. Computer-Aided Design, volume CAD-2, no. 3, pp. 180-192, July 1983.
-
(1983)
IEEE Trans. Computer-Aided Design
, vol.CAD-2
, Issue.3
, pp. 180-192
-
-
Hocevar, D.E.1
Lightner, M.R.2
Trick, T.N.3
-
7
-
-
0022597953
-
Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters
-
Jan.
-
M. A. Styblinski and L. J. Opalski, “Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters,” IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, pp. 79-89, Jan. 1986.
-
(1986)
IEEE Trans. Computer-Aided Design
, vol.CAD-5
, Issue.1
, pp. 79-89
-
-
Styblinski, M.A.1
Opalski, L.J.2
-
9
-
-
25844521485
-
Statistical performance modeling and parametric yield estimation of MOS VLSI
-
Nov.
-
T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, “Statistical performance modeling and parametric yield estimation of MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 6, pp. 1013-1022, Nov. 1987.
-
(1987)
IEEE Trans. Computer-Aided Design
, vol.CAD-6
, Issue.6
, pp. 1013-1022
-
-
Yu, T.K.1
Kang, S.M.2
Hajj, I.N.3
Trick, T.N.4
-
10
-
-
0024888770
-
An efficient method for parametric yield optimization of MOS integrated circuits
-
Nov.
-
T. K. Yu, S. M. Kang, J. Sacks, and W. J. Welch, “An efficient method for parametric yield optimization of MOS integrated circuits,” in Proc. IEEE Int. Conf. CAD, Nov. 1989, pp. 190-193.
-
(1989)
in Proc. IEEE Int. Conf. CAD
, pp. 190-193
-
-
Yu, T.K.1
Kang, S.M.2
Sacks, J.3
Welch, W.J.4
-
11
-
-
0027101112
-
Improved methods for IC yield and quality optimization using surface integrals
-
Nov.
-
P. Feldmann and S. W. Director, “Improved methods for IC yield and quality optimization using surface integrals,” in Proc. IEEE Int. Conf. CAD, Nov. 1991, pp. 158-161.
-
(1991)
in Proc. IEEE Int. Conf. CAD
, pp. 158-161
-
-
Feldmann, P.1
Director, S.W.2
-
12
-
-
0026839811
-
Integrated circuit design optimization using a sequential strategy
-
Mar.
-
M. C. Bernardo, R. Buck, L. Liu, W. Nazaret, J. Sacks, and W. J. Welch, “Integrated circuit design optimization using a sequential strategy,” IEEE Trans. Computer-Aided Design, vol. 11, no. 3, pp. 361-372, Mar. 1992.
-
(1992)
IEEE Trans. Computer-Aided Design
, vol.11
, Issue.3
, pp. 361-372
-
-
Bernardo, M.C.1
Buck, R.2
Liu, L.3
Nazaret, W.4
Sacks, J.5
Welch, W.J.6
-
13
-
-
84869995007
-
Hierarchical yield estimation of large analog integrated circuits
-
May
-
C, M. Kurker, J. J. Paulos, R. S. Gyurcsik, and J-C. Lu, “Hierarchical yield estimation of large analog integrated circuits,” in Proc. IEEE Custom Integrated Circuits Conf, May 1992, pp. 3.2.1-3.2.4.
-
(1992)
in Proc. IEEE Custom Integrated Circuits Conf
, pp. 1-4
-
-
Kurker, C, M.1
Paulos, J.J.2
Gyurcsik, R.S.3
Lu, J-C.4
-
15
-
-
0026991450
-
An integrated approach to realistic worst-case design optimization of MOS analog circuit
-
June
-
A. Dharchoudhury and S. M. Kang, “An integrated approach to realistic worst-case design optimization of MOS analog circuit,” in Proc. 29th IEEE/ACM Design Automation Conf, June 1992, 704-709.
-
(1992)
in Proc. 29th IEEE/ACM Design Automation Conf
, pp. 704-709
-
-
Dharchoudhury, A.1
Kang, S.M.2
|