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Volumn 29, Issue 3, 1994, Pages 323-327

Acceptance Sampling: An Efficient, Accurate Method for Estimating and Optimizing Parametric Yield

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MONTE CARLO METHODS; OPTIMIZATION;

EID: 0028385333     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.278356     Document Type: Article
Times cited : (27)

References (19)
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  • 4
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    • Optimal centering, tolerancing, and yield determination via updated approximations and cuts
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    • J. W. Bandler and H. L. Abdel-Malek, “Optimal centering, tolerancing, and yield determination via updated approximations and cuts,” IEEE Trans. Circuits Syst., vol. CAS-25, no. 10, pp. 853-871, Oct. 1978.
    • (1978) IEEE Trans. Circuits Syst. , vol.CAS-25 , Issue.10 , pp. 853-871
    • Bandler, J.W.1    Abdel-Malek, H.L.2
  • 5
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    • Statistical exploration approach to design centering
    • pt. G, Dec.
    • R. S. Soin and R. Spence, “Statistical exploration approach to design centering,” Proc. Inst. Elec. Eng., pt. G, vol. 127, no. 6, pp. 260-269, Dec. 1980.
    • (1980) Proc. Inst. Elec. Eng. , vol.127 , Issue.6 , pp. 260-269
    • Soin, R.S.1    Spence, R.2
  • 6
    • 0020778410 scopus 로고
    • A study of variance reduction techniques for estimating circuit yield
    • July
    • D. E. Hocevar, M. R. Lightner, and T. N. Trick, “A study of variance reduction techniques for estimating circuit yield,” IEEE Trans. Computer-Aided Design, volume CAD-2, no. 3, pp. 180-192, July 1983.
    • (1983) IEEE Trans. Computer-Aided Design , vol.CAD-2 , Issue.3 , pp. 180-192
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  • 7
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    • Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters
    • Jan.
    • M. A. Styblinski and L. J. Opalski, “Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters,” IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, pp. 79-89, Jan. 1986.
    • (1986) IEEE Trans. Computer-Aided Design , vol.CAD-5 , Issue.1 , pp. 79-89
    • Styblinski, M.A.1    Opalski, L.J.2
  • 9
    • 25844521485 scopus 로고
    • Statistical performance modeling and parametric yield estimation of MOS VLSI
    • Nov.
    • T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, “Statistical performance modeling and parametric yield estimation of MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 6, pp. 1013-1022, Nov. 1987.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , Issue.6 , pp. 1013-1022
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  • 10
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    • T. K. Yu, S. M. Kang, J. Sacks, and W. J. Welch, “An efficient method for parametric yield optimization of MOS integrated circuits,” in Proc. IEEE Int. Conf. CAD, Nov. 1989, pp. 190-193.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.