All-N-logic high-speed true-single-phase dynamic CMOS logic

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 2, 1996, Pages 221-229

  Gu, Richard X ^a,b,c,d,e,f   Elmasry, Mohamed I ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b TEXAS INSTRUMENTS   (United States)

^c Fudan University ^*

^d FUDAN UNIVERSITY   (China)

^e UNIVERSITY OF WESTERN ONTARIO   (Canada)

^f Shanghai Instituted of Technology   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FREQUENCY DIVIDING CIRCUITS; MOSFET DEVICES; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; SCHEMATIC DIAGRAMS;

CARRY GENERATOR; CMOS LOGIC; DYNAMIC CIRCUITS;

LOGIC CIRCUITS;

EID: 0030084589     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.487999     Document Type: Article

References (7)

1. R. H. Krambeck, C. M. Lee, and H.-S. Law, "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. 17, pp. 614-619, June 1982.
2. N. F. Goncalves and H. J. De Man, "NORA: A race-free dynamic CMOS technology for pipelined logic structures," IEEE J. Solid-State Circuits, vol. 18, pp. 261-266, June 1983.
3. J. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
4. C. M. Lee and E. W. Szeto, "Zipper CMOS," IEEE Circuits Devices Mag., pp. 10-16, May 1986.
5. C. Y. Wu, K. H. Cheng, and J. S. Wang, "Analysis and design of a new race-free four-phase CMOS logic," IEEE J. Solid-State Circuits, vol. 28, pp. 18-25, Jan. 1993.
6. R. X. Gu and M. I. Elmasry, "An all-N-logic high-speed single-phase dynamic CMOS logic," in Proc. ISCAS, vol. 4, London, England, May 1994, pp. 7-10.
7. M. Shoji, CMOS Digital Circuit Technology. Englewood Cliffs, NJ: Prentice-Hall, 1988.