A robust single phase clocking for low power, high-speed VLSI applications

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 2, 1996, Pages 247-254

  Afghahi, M ^a,b  

^a ERICSSON RADIO SYSTEMS AB   (Sweden)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC LOSSES; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; SYSTEMS ANALYSIS; VLSI CIRCUITS;

CLOCKING NETWORK; POWER DISSIPATION; TRUE SINGLE PHASE CLOCKING;

TIMING CIRCUITS;

EID: 0030082972     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.488002     Document Type: Article

References (16)

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