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Volumn 25, Issue 1, 2000, Pages 39-53

Automatic target recognition with dynamic reconfiguration

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS; IMAGE ANALYSIS; IMAGE QUALITY; MICROPROCESSOR CHIPS;

EID: 0033747187     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008173519198     Document Type: Article
Times cited : (2)

References (14)
  • 3
    • 0029754038 scopus 로고    scopus 로고
    • Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-based FPGAs
    • J.G. Eldrege and B.L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-based FPGAs," Journal of VLSI Signal Processing, vol. 12, pp. 67-86, 1996.
    • (1996) Journal of VLSI Signal Processing , vol.12 , pp. 67-86
    • Eldrege, J.G.1    Hutchings, B.L.2
  • 8
    • 0000341994 scopus 로고
    • Designing A Partially Reconfigured System
    • FPGAs for Fast Board Development and Reconfigurable Computing
    • J.D. Hadley and B.L. Hucthings, "Designing A Partially Reconfigured System," in FPGAs for Fast Board Development and Reconfigurable Computing, in Proc. SPIE 2607, 1995, pp. 210-220.
    • (1995) Proc. SPIE 2607 , pp. 210-220
    • Hadley, J.D.1    Hucthings, B.L.2
  • 12
    • 0003428414 scopus 로고
    • Reading, MA, USA: Addison-Wesley
    • W.R. Stevens, TCP/IP Illustrated, vol. 1, Reading, MA, USA: Addison-Wesley, 1994.
    • (1994) TCP/IP Illustrated , vol.1
    • Stevens, W.R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.