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Volumn 1998-April, Issue , 1998, Pages 1-9

Dynamic circuit generation for solving specific problem instances of Boolean satisfiability

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FORMAL LOGIC; TIMING CIRCUITS;

EID: 85049223861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707897     Document Type: Conference Paper
Times cited : (17)

References (22)
  • 2
    • 0026623575 scopus 로고
    • Test Pattern Generation Using Boolean Satisfiability
    • T. Larrabee, "Test Pattern Generation Using Boolean Satisfiability," IEEE Transactions on Computer-Aided Design, vol. 11, pp. 4-15, 1993.
    • (1993) IEEE Transactions on Computer-Aided Design , vol.11 , pp. 4-15
    • Larrabee, T.1
  • 4
    • 84881072062 scopus 로고
    • A Computing Procedure for Quantification Theory
    • M. Davis and H. Putnam, "A Computing Procedure for Quantification Theory," Journal of the ACM, vol. 7, pp. 201-215, 1960.
    • (1960) Journal of the ACM , vol.7 , pp. 201-215
    • Davis, M.1    Putnam, H.2
  • 5
    • 0019543877 scopus 로고
    • An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
    • P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Transactions on Computers, vol. C30, pp. 215-222, 1981.
    • (1981) IEEE Transactions on Computers , vol.C30 , pp. 215-222
    • Goel, P.1
  • 7
    • 0031339617 scopus 로고    scopus 로고
    • On Acceleration of the Check Tautology Logic Synthesis Algorithm using an FPGAbased Reconfigurable Coprocessor
    • Napa, CA
    • J. Cong and J. Peck, "On Acceleration of the Check Tautology Logic Synthesis Algorithm using an FPGAbased Reconfigurable Coprocessor," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, Napa, CA, 1997.
    • (1997) Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
    • Cong, J.1    Peck, J.2
  • 12
    • 84947944005 scopus 로고
    • An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
    • W. M. a. W. Luk, Ed. Oxford, England: Springer
    • R. J. Petersen and B. L. Hutchings, "An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing," in Field-Programmable Logic and Applications, W. M. a. W. Luk, Ed. Oxford, England: Springer, 1995, pp. 293-302.
    • (1995) Field-Programmable Logic and Applications , pp. 293-302
    • Petersen, R.J.1    Hutchings, B.L.2
  • 17
    • 84990479742 scopus 로고
    • An Efficient Heuristic Procedure for Partitioning Graphs
    • B. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell Systems Technical Journal, vol. 49, pp. 291-307, 1970.
    • (1970) Bell Systems Technical Journal , vol.49 , pp. 291-307
    • Kernighan, B.1    Lin, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.