Dynamic reconfiguration to support concurrent applications

IEEE Transactions on Computers

Volumn 48, Issue 6, 1999, Pages 591-602

  Jean, Jack S N ^a,b   Tomko, Karen ^a,b   Yavagal, Vikram ^b   Shah, Jignesh ^a,b   Cook, Robert ^b  

^a IEEE

^b Wright State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABLE COMPUTING; RECONFIGURATION; RESOURCE MANAGEMENT;

COMPUTATION THEORY; COMPUTER HARDWARE; CONCURRENCY CONTROL; DATA PROCESSING; MICROPROCESSOR CHIPS; RESOURCE ALLOCATION; SCHEDULING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032686440     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.773796     Document Type: Article

References (18)

1. J.G. Eldrege and B.L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs," J. VLSI Signal Processing, vol. 12, pp. 67-86, 1996.
2. J.D. Hadley and B.L. Hutchings, "Designing a Partially Reconfigured System," FPGAs for Fast Board Development and Reconfigurable Computing, Proc. SPIE 2607, pp. 210-220, 1995.
3. J. Burns, A. Donlin, J. Hogg, S. Singh, and M. Wit, "A Dynamic Reconfiguration Run-Time System," Proc. FCCM, pp. 66-75, 1997.
4. MPEG Software, Simulation Group at: http://www.mpeg.org/ MSSG/.
5. R. Cook, J. Jean, and J.S. Chen, "Accelerating MPEG-2 Encoder Utilizing Reconfigurable Computing" Proc. CERC/VIUF and IEEE Computer Society Workshop, Univ. of Dayton, Dec. 1997.
6. M.J. Gonzalez, "Deterministic Processor Scheduling," Computing Surveys, vol. 9, no. 3, pp. 173-204, Sept. 1977.
7. S. Ha and E.A. Lee, "Compile-Time Scheduling of Dynamic Constructs in Dataflow Program Graphs," IEEE Trans. Computers, vol. 46, no. 7, pp. 768-778, July 1997.
8. K. Hill, L. Foti, D. Zebe, and B. Box, "Real-Time Signal Preprocessor Trade-Off Study," Proc. IEEE Nat'l Aerospace and Electronics Conf., pp. 328-335, May 1995.
9. W.E. King, T.H. Drayer, R.W. Conners, and P. Araman, "Using MORRPH in an Industrial Machine Vision System," Proc. IEEE Symp. FPGA Custom Computing Machines, pp. 18-26, 1996.
10. I Page, "Reconfigurable Processors," invited keynote address for the Heathrow PLD Conf., Apr. 1995.
11. B. Taylor and D. MacLeod, "X Language Doc.," Giga Operations Corp., 1994.
12. V. Yavagal, "A Resource Manager for Configurable Computing Systems," MS thesis, Wright State Univ., July 1998.
13. J. Villasenor, B. Schoner, K. Chia, C. Zapata, H. Kim, C. Jones, S. Lansing, and B. Mangione-Smith, "Configurable Computing Solutions for Automatic Target Recognition," Proc. IEEE Symp. FPGA Custom Computing Machines, pp. 70-79, 1996.
14. A. Rashid, J. Leonard, and W.H. Mangione-Smith, "Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability," Proc. IEEE Symp. Field-Programmable Custom Computing Machines, Apr. 1998.
15. T.A. Sudkamp, Languages and Machines, pp. 351-353. Addison-Wesley, 1988.
16. M.J. Wirthlin and B.L. Hutchings, "Sequencing Run-Time Re-configured Hardware with Software," Proc. ACM/SIGDA Int'l Symp. FPGAs, pp. 122-128, 1996.
17. XLINK-OSProgrammer's Reference Manual. Giga Operations Corp., 1996.
18. P. Zhong, M. Martonosi, P. Ashar, and S. Malik, "Accelerating Boolean Satisfiability with Configurable Hardware," Proc. IEEE Symp. Field-Programmable Custom Computing Machines, Apr. 1998.