Hidden Markov and independence models with patterns for sequential BIST

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 359-367

  Brehelin, Laurent ^a   Gascuel, Olivier ^a   Caraux, Gilles ^a   Girard, Patrick ^a   Landrault, Christian ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; FAILURE ANALYSIS; LEARNING ALGORITHMS; MARKOV PROCESSES; MATHEMATICAL MODELS; SEMICONDUCTING SILICON; SEQUENTIAL CIRCUITS;

FAULT COVERAGE; HIDDEN MARKOV MODEL; TEST PATTERN GENERATOR;

INTEGRATED CIRCUIT TESTING;

EID: 0033741772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (13)

1. M. Abramovici, M. Breuer, and A. Friedman. Digital Systems Testing and Testable Design. 1990.
2. L. E. Baum, T. Petrie, G. Soules, and N.Weiss. A maximization technique occurring in statistical analysis of probabilistic functions in Markov chains. The Annals of Mathematical Statistics, 41(1):164-171, 1970.
3. L. Bréhélin, O. Gascuel, and G. Caraux. Hidden Markov Models with Patterns to learn boolean vector sequences; application to the built-in self-test for integrated circuits. Technical Report 99006, University of Montpellier II, LIRMM, Jan. 1999.
4. S. Chiusano, F. Corno, P. Prinetto, and M. S. Reorda. Cellular automata for deterministic sequential test pattern generation. In Proceedings of the ACM, pages 60-65, Nov. 1997.
5. F. Corno, N. Gaudenzi, P. Prinetto, and M. Sonza-Reorda. On the identification of optimal cellular automata for builtin self-test of sequential circuits. In Proceedings of the VTS, pages 424-429, 1998.
6. C. Fagot, O. Gascuel, P. Girard, and C. Landrault. On calculating efficient LFSR seeds for built-in self test. In IEEE ETW, May 1999.
7. G. D. Forney. The Viterbi algorithm. Proc. IEEE, 61(3):268-278, Mar. 1973.
8. V. Iyengar, K. Chakrabarty, and B. Murray. Built-in selftesting of sequential circuits using precomputed test sets. In Proceedings of the VTS, pages 418-423, 1998.
9. I. Pomeranz and S. M. Reddy. Built-in test generation for synchronous sequential circuits. In Proceedings of the ACM ICCAD, pages 421-427, Nov. 1997.
10. A. Stolcke and S. Omohundro. Inducing probabilistic grammars by bayesian model merging. In Proceedings of the ICGI, volume 862 of LNAI, pages 106-118, Berlin, 1994.
11. N. Touba and E. McCluskey. Altering a pseudo-random bit sequence for scan-based BIST. In Proceedings of the ITC, pages 167-175, Oct. 1996.
12. S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick. An efficient BIST scheme based on reseeding of multiple polynomial linear feedback shift registers. In Proceedings of the IEEE/ACM ICCAD, pages 572-577, Nov. 1993.
13. H.-J. Wunderlich and G. Kiefer. Bit-flipping BIST. In Proceedings of the IEEE/ACM ICCAD, pages 337-345, Nov.10-14 1996.