On the identification of optimal cellular automata for Built-In Self-Test of sequential circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn Proceedings of the IEEE VLSI Test Symposium, Issue , 1998, Pages 424-429

  Corno, F ^a   Gaudenzi, N ^a   Prinetto, P ^a   Reorda, M S ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CELLULAR ARRAYS; FINITE AUTOMATA; GENETIC ALGORITHMS; IDENTIFICATION (CONTROL SYSTEMS); INTEGRATED CIRCUIT TESTING; OPTIMIZATION;

CELLULAR AUTOMATA;

SEQUENTIAL CIRCUITS;

EID: 0032316914     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. M. Abramovici, M. A. Breuer, A. D. Friedman: Digital systems testing and testable design, Computer Science Press, New York, NY (USA), 1990
2. F. Brglez, D. Bryant, K. Kozminski, "Combinational profiles of sequential benchmark circuits," Proc. Int. Symp. on Circuits And Systems, 1989, pp. 1929-1934
3. S. Boubezari, B. Kaminska, "A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures," IEEE Trans. on Comp, Vol. 44, No. 6, Jun. 1995, pp. 805-816
4. S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda, "Cellular Automata for Sequential Test Pattern Generation in Deterministic BIST", Proc. VTS'97: IEEE VLSI Test Symposium, April 1997, pp. 60-65
5. F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca, "Advanced Techniques for GA-based sequential ATPGs," Proc. IEEE Design & Test Conf., 1996, pp. 375-379
6. F. Corno, P. Prinetto, M. Sonza Reorda, "Testable Synthesis of Control Units via Circular Self-Test Path: Problems and Solutions," IEEE Design & Test, Winter 1996, pp. 50-60
7. F. Fummi, D. Sciuto, "Implicit Test Pattern Generation Constrained to Cellular Automata Embedding," Proc. IEEE VLSI Test Symposium, 1997, pp. 54-59
8. D.E. Goldberg, "Genetic Algorithms in Search, Optimization, and Machine Learning," Addison-Wesley, 1989
9. P.D. Hortensius, R.D. McLeod, W. Pries, D.M. Miller, H.C. Card, "Cellular Automata-Based Pseudorandom Number Generators for Built-in Self-Test," IEEE Trans. on Computer-Aided Design, Vol. 8, No. 8, Aug. 1989, pp. 842-859
10. A. Krasniewski, S. Pilarski, Circular Self-Test Path: A low-cost BIST Technique for VLSI circuits, IEEE Trans. on CAD, Vol. 8, No. 1, Jan. 1989, pp. 46-55
11. T.M. Niermann, W.-T. Cheng, J.H. Patel, "PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator," IEEE Trans. on CAD, Vol. 11, No. 2, Feb. 1992, pp. 198-207
12. J. van Sas, F. Catthoor, H. De Man, "Cellular Automata Based Deterministic Self-Test Strategies for Programmable Data Paths," IEEE Trans. on CAD, Vol. 13, No. 7, Jul. 1994, pp. 940-949
13. C.E. Stroud, "Automated BIST for Sequential Logic Synthesis", IEEE Design&Test., Dec. 1988, pp. 22-32
14. S. Wolfram, "Statistical Mechanics of Cellular Automata," Rev. Mod. Phys. 55, 1983, pp. 601-644.