Power optimization method considering glitch reduction by gate sizing

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages

  Hashimoto, Masanori ^a   Onodera, Hidetoshi ^a   Tamaru, Keikichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; CMOS INTEGRATED CIRCUITS; OPTIMIZATION; PERTURBATION TECHNIQUES; STATISTICAL METHODS;

GLITCH REDUCTION;

COMBINATORIAL CIRCUITS;

EID: 0031632591     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)