Sequential circuit test generation using decision diagram models

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 736-740

  Raik, Jaan ^a   Ubar, Raimund ^a  

^a TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMITY TESTS; DECISION DIAGRAM; FAULT COVERAGES; FUNCTIONAL UNITS; LOCAL TESTS; MULTI-LEVEL DECISIONS; SEQUENTIAL CIRCUIT TEST GENERATION; STRUCTURAL FAULTS;

EXHIBITIONS;

SEQUENTIAL CIRCUITS;

EID: 84893612622     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761212     Document Type: Conference Paper

References (8)

1. T. M. Niermann, J. H. Patel, "HITEC: A test generation package for sequential circuits", Proc. of the EDAC, pp.214-218, 1991.
2. F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, "GATTO: A genetic algorithm for automatic test pattern generation for large synchronous sequential circuits", IEEE Tran. CAD, vol.15, no.8, pp.991-1000, Aug. 1996.
3. E. M. Rudnick, J. H. Patel, G. S. Greenstein, T. M. Niermann, "Sequential circuit test generation in a genetic algorithm framework", Proc. of the DAC., pp. 698-704, 1994.
4. E. M. Rudnick, R. Vietti, A. Ellis, F. Corno, P.Prinetto, M. Sonza Reorda, "Fast sequential circuit test generation using high-level and gate-level techniques", Proc. of DATE, 1998.
5. J. Lee and J.H. Patel, "Architectural level test generation for microprocessors", IEEE Trans. CAD, vol.13, no.10, pp.1288-1300, Oct. 1994.
6. R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Computers, pp. 48-57, Spring 1996.
7. R.Ubar, J.Raik, "Hierarchical test generation for digital systems based on combining bottom-up and top-down approaches", Proc. of SCI/ISAS'98, pp.374-381, Orlando, July 1998.
8. G.Jervan, A.Markus, J.Raik, R.Ubar, "DECIDER: A Decision Diagram based Hierarchical Test Generation System", Proc. of the DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998.