A simulation study of IC layout effects on thermal management of die attached GaAs ICs

IEEE Transactions on Components and Packaging Technologies

Volumn 23, Issue 2, 2000, Pages 341-351

  Reimer, Christopher J ^a   Smy, Tom ^a   Walkey, David J ^a   Beggs, B C ^b   Surridge, R ^b  

^a CARLETON UNIVERSITY   (Canada)

^b NORTEL NETWORKS   (Canada)

Author keywords

Emitter optimization; Gaas; Heat spreader; Patran, simulation; Thermal

Indexed keywords

COMPUTER SIMULATION; FINITE ELEMENT METHOD; HEAT TRANSFER; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DEVICES; SUBSTRATES; THERMAL EFFECTS; THERMODYNAMIC PROPERTIES;

GALLIUM ARSENIDE INTEGRATED CIRCUITS; HEAT SPREADER; SOFTWARE PACKAGE PATRAN; THERMAL MANAGEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033701563     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/6144.846773     Document Type: Article

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