On logic and transistor level design error detection of various validation approaches for PowerPCTM microprocessor arrays

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 260-265

  Wang, L C ^a   Abadir, M S ^a   Zeng, J ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; EFFICIENCY; EMBEDDED SYSTEMS; ERROR ANALYSIS; ERROR DETECTION; LOGIC CIRCUITS; TRANSISTORS;

ERROR SIMULATION;

MICROPROCESSOR CHIPS;

EID: 0032316632     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)