Characterization of polysilicon-gate depletion in MOS structures

IEEE Electron Device Letters

Volumn 17, Issue 3, 1996, Pages 103-105

  Ricco B ^a,b   Versari, R ^b   Esseni, D ^b  

^a IEEE

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITANCE MEASUREMENT; CHARACTERIZATION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CRYSTAL IMPURITIES; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; VOLTAGE MEASUREMENT;

DEPLETION CAPACITANCE; IMPURITY CONCENTRATION; MICROMETER TRANSISTORS; POLYSILICON; POLYSILICON GATE DEPLETION; SUBSTRATE OXIDE INTERFACE; TWO DIMENSIONAL SIMULATION;

MOSFET DEVICES;

EID: 0030110234     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.485181     Document Type: Article

References (7)

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