A 200 MHz 13 mm2 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 12, 1994, Pages 1482-1490

  Matsui, Masataka ^a   Hara, Hiroyuki ^b   Nagamatsu, Tetsu ^b   Sakurai, Takayasu ^b   Watanabe, Yoshinori ^b   Matsuda, Kouji ^b   Walanabe, Kouji ^b   Chiba, Akihiko ^b   Kim, Lee Sup ^b  

^a STANFORD UNIVERSITY   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; DATA COMPRESSION; DIFFERENTIAL AMPLIFIERS; FABRICATION; IMAGE COMPRESSION; LSI CIRCUITS; MOS DEVICES; MOSFET DEVICES; PIPELINE PROCESSING SYSTEMS; TECHNOLOGY;

BIT CARRY SKIP ADDER; CARRY LOOK AHEAD; DIFFERENTIAL SYNCHRONOUS SENSE AMPLIFIER; ITERATIVE MULTIPLIER ACCUMULATORS; TWO DIMENSIONAL DISCRETE COSINE TRANSFORM MACROCELL;

FLIP FLOP CIRCUITS;

EID: 0028733304     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.340421     Document Type: Article

References (7)

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