A 0.8 μ 100-MHz 2-D DCT core processor

IEEE Transactions on Consumer Electronics

Volumn 40, Issue 3, 1994, Pages 703-710

  Jang, Yi Feng ^a   Kao, Jinn Nang ^a   Yang, Jinn Shiang ^a   Huang, Po Chuang ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA COMPRESSION; DIGITAL ARITHMETIC; IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL TRANSFORMATIONS; MULTIPLYING CIRCUITS; RANDOM ACCESS STORAGE; TECHNOLOGY; VLSI CIRCUITS;

DISCRETE COSINE TRANSFORM; HARDWARE OVERHEAD; MULTIPLIER ACCUMULATOR; PIXEL RATE; TWO DIMENSIONAL DISCRETE COSINE TRANSFORM CORE PROCESSOR;

COMPUTER HARDWARE;

EID: 0028481156     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.320861     Document Type: Article

References (6)

1. N. Ahmed and K.R. Rao, “Orthogonal Transforms for Digital Signal Processing,” Springer-Verlag 1975, pp.169–172, 200-222.
2. J.N. Kao, “A High Speed 2-D DCT Architecture for HDTV System”, Int'l Workshop on HDTV ‘92, Val, pp. 49.1–49.6, Nov. 1992.
3. W.H. Chen, et al., “A fast computational algorithm for the discrete cosine transform,” IEEE Trans. Commun., vol. COM-25, no. 9, pp. 1004–1009, Sept. 1977
4. JC. Carlach, P. Penard, JL. Sicre, “TCAD: A 27-MHz 8x8 Discrete Cosine Transform Chip,” 1989 Intn'l Conf. on Acoust., Speech, and Signal Processing, pp. 2429–32, 1989.
5. S. I. Uramoto, et. al., “A 100-MHz 2-D Discrete Cosine Transform Core Processor,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 492–498, April 1992.
6. H. S. Hou, “A fast recursive algorithm for computing the discrete cosine transform,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-35, no. 10, pp. 1455–1461, Oct. 1987