A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 5, 1999, Pages 653-660

  Sato, Takashi ^a,b,c   Nishio, Yoji ^b   Sugano, Toshio ^b   Nakagome, Yoshinobu ^a,b  

^a IEEE   (Japan)

^b HITACHI LTD   (Japan)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bandwidth; Data transfer; Double data rate; Repetitive distributed delay (REDD); Skew; Synchronous DRAM

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; DATA TRANSFER; DELAY CIRCUITS; FREQUENCY DOMAIN ANALYSIS;

BIT-TO-BIT SKEW CONTROL; REPETITIVE DISTRIBUTED DELAY (REDD);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032648226     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.760375     Document Type: Article

References (8)

1. P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, "High-performance microprocessor design," IEEE J. Solid-Sate Circuits, vol. 33, pp. 676-686, May 1998.
2. J. Silberman, N. Aoki, D. Boerstler, J. Burns, S. Dhong, A. Essbaum, U. Ghoshal, D. Heidel, P. Hofstee, K. Lee, D. Meltzer, H. Ngo, K. Nowka, S. Posluszny, and O. Takahashi, "A 1.0 GHz single-issue 64b PowerPC integer processor," in 1998 ISSCC Dig. Tech. Papers, FP 15.1, Feb. 1998, pp. 230-231.
3. T. Sato, Y. Nishio, T. Sugano, and Y. Nakagome, "5 GByte/s data transfer scheme with bit-to-bit skew control for synchronous DRAM," in IEEE 1998 Symp. VLSI Circuits Dig. Tech. Papers, June 1998, pp. 64-65.
4. B. S. Song and D. C. Soo, "NRZ timing recovery technique for band-limited channels," in 1996 ISSCC Dig. Tech. Papers, FP 12.1, Feb. 1996, pp. 194-195.
5. C. Kim, J. Lee, B. Kim, C. Park, S. Lee, C. Park, J. Roh, H. Nam, D. Kim, T. Jung, and S. Cho, "A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system," in 1998 ISSCC Dig. Tech. Papers, FA 10.2, Feb. 1998, pp. 158-159.
6. T. Hamamoto, M. Tsukude, K. Arimoto, Y. Konishi, T. Miyamoto, H. Ozaki, and M. Yamada, "400-MHz random column operating SDRAM techniques with self-skew compensation," IEEE J. Solid-State Circuits, vol. 33, pp. 770-778, May 1998.
7. R. K. Poon, Computer Circuits Electrical Design. New York: Prentice-Hall, 1995, pp. 143-145.
8. T. J. Gabara, W. C. Fisher, J. Harrington, and W. W. Troutman, "Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers," IEEE J. Solid-Sate Circuits, vol. 32, pp. 407-417, May 1997.