A Switch-Level Model and Simulator for MOS Digital Systems

IEEE Transactions on Computers

Volumn C-33, Issue 2, 1984, Pages 160-177

  Bryant, Randal E ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

MOS logic simulation switch level model VLSI

Indexed keywords

MOS LOGIC SIMULATION; SWITCH-LEVEL MODEL;

LOGIC CIRCUITS;

EID: 0021377624     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1984.1676408     Document Type: Article

References (24)

1. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
2. G. Sakauye et al., “A set of programs for MOS design,” in Proc. 18th Ass. Comput. Mach. Design Automat. Conf., 1981, pp. 435–441.
3. W. Sherwood, “A MOS modelling technique for 4-state true-value hierarchial logic simulation,” in Proc. 18th Ass. Comput. Mach. Design Automat. Conf., 1981, pp. 775–785.
4. D. Holt and D. Hutchings, “A MOS/LSI oriented logic simulator,” in Proc. 18th Ass. Comput. Mach. Design Automat. Conf., 1981, pp. 280–287.
5. R. Bryant, A Switch-Level Simulation Model for Integrated Logic Circuits, Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge, MA, 1981.
6. '‘'‘A switch-level model of MOS logic circuits,” in VLSI 81. New York: Academic, Aug. 1981, pp. 329–340.
7. J. Hayes, “A logic design theory for VLSI,”in Proc. 2nd Caltech Conf. VLSI, California Institute of Technology, 1981, pp. 455–476.
8. “A unified switching theory with applications to VLSI design,” Proc. IEEE, vol. 70, Oct. 1982, pp. 1140–1151.
9. R. Bryant, “MOSSIM: A switch-level simulator for MOS LSI,” in Proc. 18th Ass. Comput. Mach. Design Automat. Conf., 1981, pp. 786–790.
10. C. Baker and C. Terman, “Tools for verifying integrated circuit designs,” Lambda Magazine, 4th Quarter 1980, pp. 22–30.
11. R. Bryant, M. Schuster, and D. Whiting, MOSSIM II: A Switch-Level Simulator for MOS LSI, User’s Manual. Dept. Comput. Sci., California Inst. Technol., 1982.
12. J. Bfzozowski and M. Yoeli, “On a ternary model of gate networks,” IEEE Trans. Comput., vol. C-28, Mar. 1979, pp. 178–183.
13. M. Breuer, “A note on three-valUed logic simulation,” IEEE Trans. Comput., vol. C-22, Apr. 1972, pp. 399–402.
14. M. Yoeli and S. Rinon, “Application of ternary algebra to the study of static hazards,” J. Ass. Comput. Mach., vol. 11–1, Jan. 1964, pp. 84–97.
15. M. Garey and D. Johnson, Computers and Intractibility: A guide to the Theory of NP-Completeness. San Francisco: Freeman, 1979.
16. J. Ullman, Computational Aspects of VLSI Design. New York: Computer Science, 1983.
17. R. Bryant, “An algorithm for MOS logic simulation,” Lambda Magazine, 4th Quarter 1980, 46–53.
18. C. Liu, Introduction to Combinatorial Mathematics. New York: McGraw-Hill, 1968.
19. A. Aho, J. Hopcroft, and J. Ullman, The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1974.
20. G. Birkhoff, Lattice Theory. American Mathematical Society, 1967.
21. D. Scott, “Continuous lattices,” in Toposes, Algebraic Logic, and Logic. Berlin: Springer-Verlag, 1972.
22. Mainsail Language Manual. Xidak Inc., Menlo Park, CA, 1982.
23. G. Pfister, “The Yorktown simulation engine, introduction,” in Proc. 19th Ass. Comput. Mach. Design Automat. Conf., 1982, pp: 51–54.
24. Z. Barzilai et al., “Simulating pass transistor circuits using logic simulation machines,” in Proc. 20th Ass. Comput. Mach. Design Automat. Conf., 1983, pp. 157–163.