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Volumn 6, Issue , 1999, Pages

Equivalence classes of clone circuits for physical-design benchmarking

Author keywords

[No Author keywords available]

Indexed keywords

CLONE CIRCUITS;

EID: 0032633663     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article
Times cited : (3)

References (16)
  • 2
    • 84883779212 scopus 로고    scopus 로고
    • Logic synthesis and optimization b'enchmarks
    • Research Triangle Park, NC. See also NCSU CAD Benchmarking Laboratory
    • S. Yang, "Logic synthesis and optimization b'enchmarks" V3.0, Tech. Report, Microelectronics Center of North Carolina, Research Triangle Park, NC. See also NCSU CAD Benchmarking Laboratory at http://www.cbl.ncsu.edu.
    • V3.0, Tech. Report, Microelectronics Center of North Carolina
    • Yang, S.1
  • 6
    • 0032182384 scopus 로고    scopus 로고
    • Characterization and parameterized generation of synthetic combinational benchmark circuits
    • Oct
    • M. D. Hutton, J. P. Grossman, J. Rose, and D. G. Corneil, "Characterization and parameterized generation of synthetic combinational benchmark circuits" IEEE Trans. CAD of Integrated Circuits and Systems, vol. 17, no. 10, Oct, 1998, 149- 155.
    • (1998) IEEE Trans. CAD of Integrated Circuits and Systems , vol.17 , Issue.10 , pp. 149-155
    • Hutton, M.D.1    Grossman, J.P.2    Rose, J.3    Corneil, D.G.4
  • 8
    • 0029702218 scopus 로고    scopus 로고
    • A method for generating random circuits and its application to routability measurement
    • Feb
    • J. Darnauer and W. Dai, "A method for generating random circuits and its application to routability measurement,''' in Proc. 4'h ACMISIGDA Int. Symp. FPGAs (FPGA96), Feb 1996, pp 66-72.
    • (1996) Proc. 4'h ACMISIGDA Int. Symp. FPGAs (FPGA96) , pp. 66-72
    • Darnauer, J.1    Dai, W.2
  • 9
    • 0018453798 scopus 로고
    • Placement a:nd average interconnection lengths of computer logic
    • W. E. Donath, "Placement a:nd average interconnection lengths of computer logic" IEEE Trans. Cornput., vol. C-26, no. 4, pp 272-277, 1979.
    • (1979) IEEE Trans. Cornput. , vol.C-26 , Issue.4 , pp. 272-277
    • Donath, W.E.1
  • 10
    • 0015206785 scopus 로고
    • On a pin versus bla'ck relationship for partitions of logic graphs
    • B. S. Landman and R. L. Russo, "On a pin versus bla'ck relationship for partitions of logic graphs" IEEE Trails. Cornput., vol C-20, no. 12, pp. 1469-1479, 1971.
    • (1971) IEEE Trails. Cornput. , vol.C-20 , Issue.12 , pp. 1469-1479
    • Landman, B.S.1    Russo, R.L.2
  • 11
    • 0028573039 scopus 로고
    • Random generation of tlest instances for logic optimizers
    • K. Iwama and K. Hino, "Random generation of tlest instances for logic optimizers" in Proc. 31"' Design Automation Conf. (DAC), 1994, pp. 430-434.
    • (1994) Proc. 31"' Design Automation Conf. (DAC) , pp. 430-434
    • Iwama, K.1    Hino, K.2
  • 12
    • 0030717794 scopus 로고    scopus 로고
    • Towards a new benchmarking paradigm in EDA: Analysis of equivalence class mutant circuit distributions
    • April
    • N. Kapur, D. Ghosh and F. Brglez, "Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions" in Proc. ACM International Symposium on Physical Design, April, 1997.
    • (1997) Proc. ACM International Symposium on Physical Design
    • Kapur, N.1    Ghosh, D.2    Brglez, F.3
  • 14
    • 0009973892 scopus 로고    scopus 로고
    • Synthesis of wiring-signature-invariant equivalence class cir'cuit mutants and appications to benchmarking
    • Feb.
    • D. Ghosh, N. Kapur, J. Harlow and F. Brglez, "Synthesis of wiring-signature-invariant equivalence class cir'cuit mutants and appications to benchmarking"in Proc. Design Automation and lest in Europe (DATE), Feb. 1998, pp. 656-663.
    • (1998) Proc. Design Automation and Lest in Europe (DATE) , pp. 656-663
    • Ghosh, D.1    Kapur, N.2    Harlow, J.3    Brglez, F.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.