Applications of clone circuits to issues in physical-design

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1999, Pages

  Hutton, Michael D ^a   Rose, Jonathan ^a  

^a ALTERA CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLONE CIRCUITS;

BENCHMARKING; EQUIVALENCE CLASSES; EQUIVALENT CIRCUITS;

COMPUTER AIDED NETWORK ANALYSIS;

EID: 0032625019     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (14)

1. M. D. Hutton and J. Rose, "Equivalence classes of clone circuits for physical design benchmarking," inProc. 1999 Int. Symp. Circuits and Systems (ISCAS99), Orlando, Florida, 1999.
2. M. D. Hutton, J. P. Grossman, J. Rose, and D. G. Corneil, "Characterization and parameterized generation of synthetic combinational benchmark circuits," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 17, no. 10, Oct, 1998, pp. 985-996.
3. th ACM/SIGDA Int. Symp. FPGAs, (FPGA97), Feb. 1997, pp 149-155.
4. S. Yang, "Logic synthesis and optimization benchmarks," v. 3.0 Tech. Rep., Microelectronics Center of North Carolina, Research Triangle Park, NC. Available on the MCNC website at http://www.cbl.ncsu.edu.
5. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," in Proc. 7th Int. Conf. Field-Programmable Logic, Aug. 1997. pp 213-222. See also http://www.eecg.toronto.edu/~jayar/.
6. V. Betz, J. Rose and A. Marquardt, "Architecture cind CAD for deep-submicron FPGAs," Kluwer Academic Publishers, 1999. ISBN 0-7923-8460-1.
7. th IEEE Design Automation Conference (DAC)," 1982, pp. 175-181.
8. C. Alpert, Personal website of partitioning benchmarks and partitioning code at http://vlsicad.cs.ucla.edu/~cheese.
9. th IEEE Design Automation Conference (DAC), 1997, pp. 526-529. (To appear, IEEE Trans, on VLSI Systems."
10. G. Karypis and V. Kumar, 'hMetis: a hypergraph partitioning package, VI.5.3," University of Minnesota, Department of Computer Science and Engineering, Amy HPC Research Center, Minneapolis, MN 55455. Nov. 1998.
11. M. R. Spiegel, "Theory and problems of probability and statistics - SI (metric) ed.", mcGraw-Hill, Singapore, 1980.
12. Y. Sankar and J. Rose, "Trading quahty for compile time: ultra-fast placement for FPGAs," To appear, Proc ACM/SIGDA Int. Symp. FPGAs (FPGA99 ), Feb, 1999.
13. J. Swartz, V. Betz, and J, Rose, "A fast routabihty-driven router for FPGAs," In Proc 6"' ACM/SIGDA Int. Symp. FPGAs (FPGA98), Feb, 1998. pp. 140-149.
14. J. Darnauer and W. Dai, "A method for generating random circuits and its application to routabihty measurement," in Proc. 4'" ACM/SIGDA Int. Symp. FPGAs (FPGA96), Feb 1996, pp 66-72.