![]() |
Volumn , Issue , 1997, Pages 149-155
|
Generation of synthetic sequential benchmark circuits
a
|
Author keywords
[No Author keywords available]
|
Indexed keywords
ALGORITHMS;
COMBINATORIAL CIRCUITS;
COMPUTER ARCHITECTURE;
COMPUTER SOFTWARE;
LOGIC DESIGN;
LOGIC GATES;
PARALLEL PROCESSING SYSTEMS;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
SYNTHETIC SEQUENTIAL BENCHMARK CIRCUITS;
SEQUENTIAL CIRCUITS;
|
EID: 0030695767
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/258305.258333 Document Type: Conference Paper |
Times cited : (16)
|
References (9)
|