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Volumn 16, Issue 1, 1999, Pages 71-79

Estimating the economic benefits of DFT

Author keywords

[No Author keywords available]

Indexed keywords

REVENUE RETURNS;

EID: 0032632946     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.748807     Document Type: Article
Times cited : (9)

References (13)
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  • 3
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    • Real Test Engineers Shouldn't Do DAT (Because Real Designers Don't Do Test Equipment)
    • Section 3.2, VLSI Research Inc., San Jose, Calif.
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  • 4
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    • A Test Economics Model and Cost-Benefits Analysis of Boundary Scan
    • Springer-Verlag, New York
    • J. Miles, R.D. Bondt, and L. Daemen, "A Test Economics Model and Cost-Benefits Analysis of Boundary Scan," Proc. Second European Test Conf., Springer-Verlag, New York, 1991, pp. 375-384.
    • (1991) Proc. Second European Test Conf. , pp. 375-384
    • Miles, J.1    Bondt, R.D.2    Daemen, L.3
  • 5
    • 0031341136 scopus 로고    scopus 로고
    • Testing the 400MHz IBM Generation-4 CMOS Chip
    • IEEE CS Press
    • T.G. Foote et al., "Testing the 400MHz IBM Generation-4 CMOS Chip," Proc. IEEE Int'l Test Conf., IEEE CS Press, 1997, pp. 106-114.
    • (1997) Proc. IEEE Int'l Test Conf. , pp. 106-114
    • Foote, T.G.1
  • 6
    • 0029493120 scopus 로고
    • Test Generation and Design for Test for a Large Multiprocessing DSP
    • IEEE CS Press
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    • (1995) Proc. IEEE Int'l Test Conf. , pp. 149-156
    • Hetherington, G.1
  • 7
    • 0031191267 scopus 로고    scopus 로고
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    • July-Sept.
    • J.M. Miranda, "A BIST and Boundary-Scan Economics Framework," IEEE Design & Test of Computers, Vol. 14, No. 3, July-Sept. 1997, pp. 17-23.
    • (1997) IEEE Design & Test of Computers , vol.14 , Issue.3 , pp. 17-23
    • Miranda, J.M.1
  • 8
    • 27844540046 scopus 로고
    • Test Cost Modelling Techniques and Costs
    • A.P. Ambler, M. Abadir, and S. Sastry, eds., Ellis Horwood, New York
    • C. Dislis, A.P. Ambler, and J. Dick, "Test Cost Modelling Techniques and Costs," in Economics of Design and Test for Electronic Circuits and Systems, A.P. Ambler, M. Abadir, and S. Sastry, eds., Ellis Horwood, New York, 1992, pp. 187-202.
    • (1992) Economics of Design and Test for Electronic Circuits and Systems , pp. 187-202
    • Dislis, C.1    Ambler, A.P.2    Dick, J.3
  • 9
    • 0031387345 scopus 로고    scopus 로고
    • To DFT or Not to DFT?
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    • Wei, S.1
  • 10
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    • Overhead in Scan and Self-Testing Designs
    • IEEE CS Press
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    • Ohletz, M.J.1    Williams, T.W.2    Mucha, J.P.3
  • 12
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.