메뉴 건너뛰기




Volumn 14, Issue 3, 1997, Pages 17-23

A BIST and boundary-scan economics framework

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER DEBUGGING; COST EFFECTIVENESS; ERROR CORRECTION; HIERARCHICAL SYSTEMS; INDUSTRIAL ECONOMICS; INTEGRATED CIRCUIT LAYOUT;

EID: 0031191267     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.605988     Document Type: Article
Times cited : (14)

References (8)
  • 3
    • 0027668648 scopus 로고
    • Boundary Scan Eases Test of New Technologies
    • Autumn
    • B. Johnson, "Boundary Scan Eases Test of New Technologies," Test and Measurement Europe, Autumn 1993.
    • (1993) Test and Measurement Europe
    • Johnson, B.1
  • 4
    • 85081465967 scopus 로고
    • The Economics of Design for Test: Applications Clarify the Cost of Test
    • Nov.
    • A.P. Ambler et al., "The Economics of Design for Test: Applications Clarify the Cost of Test," Evaluation Engineering, Nov. 1994, pp. 22, 23, 26.
    • (1994) Evaluation Engineering , pp. 22
    • Ambler, A.P.1
  • 5
    • 3643100149 scopus 로고
    • 3B21D BIST/Boundary-Scan System Diagnostic Test Story
    • IEEE Computer Society Press, Los Alamitos, Calif.
    • E.C. Behnke, "3B21D BIST/Boundary-Scan System Diagnostic Test Story," Proc. 1994 Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1994, pp. 120-126.
    • (1994) Proc. 1994 Int'l Test Conf. , pp. 120-126
    • Behnke, E.C.1
  • 6
    • 85081462866 scopus 로고
    • Cray Research Beats the Market with Boundary-Scan
    • Fall
    • J. West, "Cray Research Beats the Market with Boundary-Scan," Windows, A Teradyne Quarterly Publication, Vol. 8, No. 3, Fall 1995, pp. 2-4.
    • (1995) Windows, a Teradyne Quarterly Publication , vol.8 , Issue.3 , pp. 2-4
    • West, J.1
  • 7
    • 0030398939 scopus 로고    scopus 로고
    • Backplane Interconnect Test in a Boundary-Scan Environment
    • IEEE CS Press
    • W. Ke, "Backplane Interconnect Test in a Boundary-Scan Environment," Proc. 1996 Int'l Test Conf., IEEE CS Press, 1996, pp. 717-724.
    • (1996) Proc. 1996 Int'l Test Conf. , pp. 717-724
    • Ke, W.1
  • 8
    • 0038416253 scopus 로고
    • Getting to the Market on Time
    • Apr.
    • B.C. Cole, "Getting to the Market on Time," Electronics, Apr. 1989, pp. 62-66.
    • (1989) Electronics , pp. 62-66
    • Cole, B.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.