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Volumn 14, Issue 3, 1997, Pages 17-23
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A BIST and boundary-scan economics framework
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Author keywords
[No Author keywords available]
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Indexed keywords
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
COMPUTER AIDED SOFTWARE ENGINEERING;
COMPUTER ARCHITECTURE;
COMPUTER DEBUGGING;
COST EFFECTIVENESS;
ERROR CORRECTION;
HIERARCHICAL SYSTEMS;
INDUSTRIAL ECONOMICS;
INTEGRATED CIRCUIT LAYOUT;
BOUNDARY SCAN;
BUILT IN SELF TEST (BIST);
DESIGN FOR TESTABILITY (DFT);
FAILURE MODE ANALYSIS (FMA);
IN CIRCUIT TESTING (ICT);
INTEGRATED CIRCUIT TESTING;
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EID: 0031191267
PISSN: 07407475
EISSN: None
Source Type: Journal
DOI: 10.1109/54.605988 Document Type: Article |
Times cited : (14)
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References (8)
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