Diagnostic test generation procedure for combinational circuits based on test elimination

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 486-491

  Pomeranz, Irith ^a   Fuchs, W Kent ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT DETECTION TESTS;

FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING;

COMBINATORIAL CIRCUITS;

EID: 0032297995     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. P. Camurati, D. Medina, P. Prinetto and M. Sonza Reorda, "A Diagnostic Test Pattern Generation Algorithm", in Proc. Intl. Test Conf., 1990, pp. 52-58.
2. T. Ginning, U. Mahlstedt and H. Koopmeiners, "DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits", in Proc. Intl. Conf. on Computer-Aided Design, Nov. 1991, pp. 194-197.
3. G. Cabodi, P. Camurati, F. Corno, P. Prinetto and M. S. Reorda, "GARDA: A Diagnostic ATPG for Large Synchronous Sequential Circuits", in Proc. Europ. Design&Test Conf., March 1995, pp. 267-271.
4. I. Hartanto, V. Boppana, J. H. Patel and W. K. Fuchs, "Diagnostic Test Patterns Generation for Sequential Circuits", in Proc. 1997 VLSI Test Symp., April 1997, pp. 196-202.
5. S. Seshu, "On an Improved Diagnosis Program", IEEE Trans, on Electronic Computers, Feb. 1965, pp. 76-79.
6. T. J. Snethen, "Simulator-Oriented Fault Test Generator", in Proc. 14th Design Automation Conf., June 1997, pp. 88-93.
7. I. Pomeranz and S. M. Reddy, "A Diagnostic Test Generation Procedure for Synchronous Sequential Circuits Based on Test Elimination", in Proc. 1998 Intl. Test Conf.
8. S. M. Reddy, I. Pomeranz and S. Kajihara "Compact Test Sets for High Defect Coverage", IEEE Trans, on Computer-Aided Design, Aug. 1997, pp. 923-930.