Simulator-oriented fault test generator

Proceedings - Design Automation Conference

Volumn , Issue , 1977, Pages 88-93

  Snethen, Thomas J ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; TESTING; COMPUTER NETWORKS; LOGIC CIRCUITS - TESTING; LOGIC DEVICES - GATES;

COMBINATIONAL LOGIC; DIRECT MEASUREMENT; FAULT TESTS; PATTERN SEQUENCES; PSEUDO RANDOM PATTERN; SEQUENTIAL LOGIC; TEST GENERATION ALGORITHM; TEST PATTERN GENERATIONS; FAULT TEST GENERATORS;

COMPUTER CIRCUITS; INTEGRATED CIRCUITS;

EID: 0017417099     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. W. G. Bouricius, E. P. Hsieh, G. R. Putzolu, J. P. Roth, P. R. Schneider, and C. J. Tan, "Algorithms for Detection of Faults in Logic Circuits," IEEE Trans. Computers, vol. C-20, pp. 1258-1264, November 1971.
2. H. D. Schnurmann, E. Lindbloom, and R. G. Carpenter, "The Weighted Random Test-Pattern Generator," IEEE Trans. Computers, vol. C-24, pp. 695-700, July 1975.
3. D. M. Schuler, E. G. Ulrich, T. E. Baker, and S. P. Bryant, "Random Test Generator Using Concurrent Logic Simulation," Proc. 12th Design Automation Conference, pp. 261-267, June 1975.
4. J. P. Roth, "Diagnosis of Automata Failures: A Calculus and a Method," IBM J. Res. Dev., vol. 10, pp. 278-291, 1966. .