BIST structure to test delay faults in a scan environment

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 435-439

  Girard, P ^a   Landrault, C ^a   Moreda, V ^a   Pravossoudovitch, S ^a   Virazel, A ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY FAULT TESTING; STUCK-AT FAULTS;

BUILT-IN SELF TEST; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0032292138     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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