Applying two-pattern tests using scan-mapping

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 393-397

  Touba, Nur A ^a   McCluskey, Edward J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; FAILURE ANALYSIS; LOGIC DESIGN;

COMBINATIONAL MAPPING LOGIC; FAULT COVERAGE; SCAN MAPPING; TWO PATTERN TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0029724458     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)