Optimized BIST test pattern generator for delay testing

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 94-100

  Girard, P ^a   Landrault, C ^a   Moreda, V ^a   Pravossoudovitch, S ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION;

BUILT IN SELF TESTING (BIST); CIRCUIT UNDER TEST (CUT); PATH DELAY FAULTS; TEST PATTERN GENERATION;

LOGIC CIRCUITS;

EID: 0030672599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)