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Volumn 5, Issue 2, 1997, Pages 12-20
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Synthesis of asynchronous CMOS circuits with negative gates
a
a
CSEM
(Switzerland)
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Author keywords
[No Author keywords available]
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Indexed keywords
ASYNCHRONOUS SEQUENTIAL LOGIC;
BOOLEAN FUNCTIONS;
ELECTRIC NETWORK ANALYSIS;
SEMICONDUCTOR DEVICE MODELS;
STATE ASSIGNMENT;
NEGATIVE GATES;
RACE FREE CIRCUITS;
CMOS INTEGRATED CIRCUITS;
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EID: 0031185810
PISSN: 01049631
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
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Times cited : (5)
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References (25)
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