An attempt to explain thermally induced soft failures during low level ESD stresses: Study of the differences between soft and hard NMOS failures

Microelectronics Reliability

Volumn 38, Issue 11, 1998, Pages 1763-1772

  Salome, P ^a,c   Leroux, C ^a   Mariolle, D ^a   Lafond, D ^a   Chante, J P ^b   Crevel, P ^c   Reimbold, G ^a  

^a CEA LETI   (France)

^b UNIVERSITÉ DE LYON   (France)

^c Matra MHS TEMIC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC FORCE MICROSCOPY; ELECTRIC DISCHARGES; ELECTROSTATICS; FAILURE ANALYSIS; SEMICONDUCTING SILICON; SHORT CIRCUIT CURRENTS; THERMAL EFFECTS;

ELECTROSTATIC DISCHARGE;

MOSFET DEVICES;

EID: 0032204213     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(98)00179-6     Document Type: Article

References (32)

1. Amerasekera A, Werwej JF. ESD in integrated circuits. Quality Reliability Engng Int 1992;8(3):259-72.
2. Merrill R, Issaq E. ESD design methodology. In: Electrical Overstress/Electrostatic Discharge Symposium, Orlando, Florida. New York: ESD Association, 1993:233-237.
3. Duvvury C, Amerasekera A. ESD: a pervasive reliability concern for IC technologies. Proc IEEE 1993;81(5):690-702.
4. Amerasekera A, Duvvury C. The impact of technology scaling on ESD robustness and protection circuit design. In: Electrical Overstress/Electrostatic Discharge Symposium, Las Vegas, Nevada. New York: ESD Association, 1994:237-245.
5. Diaz CH, Kang SM, Duvvury C. Modeling of electrical overstress in integrated circuits. ISBN: 0-7923-9505-0. Boston: Kluwer, 1995:148.
6. Duvvury C, Amerasekera A. State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs. Semicond Sci Technol 1996;11:833-50.
7. Amerasekera A, van den Abeelen W, van Roozendaal L, Hannemann M, Schofield P. ESD failure modes: characteristic, mechanism, and process influences. IEEE Trans Electron Dev 1992;39(2):430-6.
8. Amerasekera A, van Roozendaal L, Abderhalden J, Bruines J, Sevat L. An analysis of low voltage ESD damage in advanced CMOS processes. In: Electrical Overstress/Electrostatic Discharge Symposium, Orlando, Florida. New York: ESD Association, 1990:143-150.
9. Pierce DG. Modeling metallization burnout of integrated circuits. In: Electrical Overstress/Electrostatic Discharge Symposium, Orlando, Florida. New York: ESD Association, 1982:56-61.
10. Banerjee K, Amerasekera A, Hu C. Characterization of VLSI circuit interconnect heating and failure under ESD conditions. IEEE International Reliab Phys Symp, Dallas, Texas. Piscataway: Electron Device Society of the IEEE, 1996:237-245.
11. Reiner JC. Latent gate oxide defects caused by CDMESD. In: Electrical Overstress/Electrostatic Discharge Symposium, Phoenix, Arizona. New York: ESD Association, 1995:311-321.
12. Amerasekera A, van Roozendaal L, Bruines J, Kuper F. Characterization and modeling of second breakdown in NMOSTs for the extraction of BSD-related process and design parameters. IEEE Trans Electron Dev 1991;38(9):2161-8.
13. Amerasekera A, Seitchik JA. Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions. IEEE International Electron Devices Meeting. Piscataway: Electron Device Society of the IEEE, 1994:455-458.
14. Hannemann M, Amerasekera A. Photon emission as a tool for ESD failure localization and as a technique for studying ESD phenomena. In: European Symp on Reliab of Electron Device Failure Phy and Anal, Valenzano, Italy, 1990:77-83.
15. Ohtani S, Yoshida M, Kitagawa N, Saitoh T. Model of leakage current in LDD output MOSFET due to low level ESD stress. In: Electrical Overstress/Electrostatic Discharge Symposium, Orlando, Florida. New York: ESD Association, 1990:177-181.
16. Kuper FG, Luchies JM, Bruines J. Suppression and origin of soft ESD failures in a submicron CMOS process. J Electrostatics 1994;33:315-25.
17. Kuper FG, Luchies JM, Bruines J. Suppression of soft ESD failures in a submicron CMOS process. In: Electrical Overstress/Electrostatic Discharge Symposium, Orlando, Florida. New York: ESD Association, 1993:117-122.
18. Wada T. Study of ESD evaluation methods for charged device model. In: Electrical Overstress/Electrostatic Discharge Symposium, Phoenix, Arizona. New York: ESD Association, 1995:186-193.
19. Luchies JM. PhD thesis, Twente University. ISBN 90-9008517-3, 1995.
20. Wada T. Study of the soft leakage current induced ESD on LDD transistor. Micro Reliab J 1996;36(1112):1707-10.
21. Duvvury C, Rountree RN, Stiegler HJ, Polgreen T, Corum C. ESD phenomena in graded junction devices. In: IEEE International Reliab Phys Symp Phoenix, Arizona. Piscataway: Electron Device Society of the IEEE, 1989:71-76.
22. Scott DB, Hunter WR, Shichijo H. A transmission line model for silicided diffusions: impact on the performance of VLSI circuits. IEEE Trans Electron Dev 1982;ED-29(4):651-61.
23. Scott DB, Gilles G, Hall J. A lumped element model for simulation of ESD failures in silicided devices. In: Electrical Overstress/Electrostatic Discharge Symposium, Las Vegas, Nevada. New York: ESD Association, 1986:41-47.
24. DeChiaro LF. Device ESD susceptibility testing and design hardening. In: Electrical Overstress/Electrostatic Discharge Symposium, Philadelphia, Pennsylvania, 1984:179-188.
25. Duvvury C, Rountree R. Output ESD protection techniques for advanced CMOS processes. In: Electrical Overstress/Electrostatic Discharge Symposium, Anaheim, California. New York: ESD Association, 1988:206-211.
26. Krieger G. Nonuniform ESD current distribution due to improper metal routing. In: Electrical Overstress/ Electrostatic Discharge Symposium, Las Vegas, Nevada. New York: ESD Association, 1991:104-109.
27. EOS/ESD Association Standard human body model (HBM) component level. EOS/ESD-S5.1-1993.
28. Maloney TJ, Khurana N. Transmission line pulsing techniques for circuit modeling of ESD phenomena. In: Electrical Overstress/Electrostatic Discharge Symposium, Minneapolis, Minnesota. New York: ESD Association, 1985:49-54.
29. Dwyer VM, Franklin AJ, Campbell DS. Thermal failure in semiconductor devices. Solid St Electron 1990;33(5):553-60.
30. Salomé P, Leroux C, Chante JP, Crevel P, Reimbold G. Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool. In: IEEE International Reliab Phys Symp, Denver, Colorado. Piscataway: Electron Device Society of the IEEE, 1997:325-332.
31. Chaine M, Smith S, Bui A. Unique ESD Failure Mechanisms during Negative to VCC HBM Tests. In: Electrical Overstress/Electrostatic Discharge Symposium, Santa Clara, California. New York: ESD Association, 1997:346-355.
32. Never JM, Voldman SH. Failure analysis of shallow trench isolated ESD structures. In: Electrical Overstress/ Electrostatic Discharge Symposium, Phoenix, Arizona. New York: ESD Association, 1995:273-288.