New clock-feedthrough compensation scheme for switched-current circuits

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 11, 1998, Pages 1508-1511

  Min, Byung Moo ^a   Kim, Soo Won ^a  

^a Korea University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; MOS DEVICES;

CLOCK-FEEDTHROUGH (CFT) PROBLEM;

CMOS INTEGRATED CIRCUITS;

EID: 0032203832     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.735364     Document Type: Article

References (6)

1. C. Toumazou, J.B. Hughes, and N. C. Battersby, Eds., Switched-Currents, An Analogue Technique for Digital Technology. London, U.K.: Peregrinus, 1993.
2. T.S. Fiez and D. J. Allstot, Switched-current circuit design issues, IEEE J. Solid-State Circuits, vol. 26, pp. 192-202, 1991.
3. H.C. Yang, T. S. Fiez, and D. J. Allstot, Current-feedthrough effects and cancellation techniques in switched-current circuits, in Proc. IEEE Int. Symp. Circuits and Systems May 1990, pp. 3186-3188.
4. M. Song, Y. Lee, and W. Kim, A clock feedthrough reduction circuit for switched-current systems, IEEE J. Solid-State Circuits, vol. 28, pp. 133-137, 1993.
5. B. Jonsson and S. Eriksson, New clock-feedthrough compensation scheme for switched-current circuits, Electron. Lett., vol. 29, pp. 1446-1447, 1993.
6. M. Helfenstein and G.S. Moschytz, Clockfeedthrough compensation technique for switched-current circuits, IEEE Trans. Circuits Syst. II vol. 42, pp. 229-231, Mar. 1995.