Self-timed method to minimize spurious transitions in low power CMOS circuits

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1994, Pages 62-63

  Ko, Uming ^a   Balsara, P T ^a   Lee, Wai ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ELECTRIC LOADS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC DESIGN; PERFORMANCE; POWER CONTROL;

LOW POWER SELF TIMED DOUBLE PASS GATE LOGIC; POWER MINIMIZATION; SPURIOUS TRANSITIONS;

CMOS INTEGRATED CIRCUITS;

EID: 0028736834     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)