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Volumn , Issue , 1997, Pages 290-297

Designing networks with error detection properties through the fault-error relation

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ENCODING (SYMBOLS); ERROR ANALYSIS; ERROR DETECTION;

EID: 0031364103     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1997.628336     Document Type: Conference Paper
Times cited : (10)

References (16)
  • 1
    • 0017982079 scopus 로고
    • Strongly Fault Secure Logic Networks
    • J. E. Smith G. Metze Strongly Fault Secure Logic Networks IEEE Trans. Comput. C-27 6 491 499 June 1978
    • (1978) IEEE Trans. Comput. , vol.C-27 , Issue.6 , pp. 491-499
    • Smith, J.E.1    Metze, G.2
  • 3
    • 0028368609 scopus 로고
    • Self-checking Combinational Circuit Design for Single and Unidirectional Multibit Error
    • F. Busaba P. K. Lala Self-checking Combinational Circuit Design for Single and Unidirectional Multibit Error Journal of Electronic Testing: Theory and Applications 5 19 28 1994
    • (1994) Journal of Electronic Testing: Theory and Applications , Issue.5 , pp. 19-28
    • Busaba, F.1    Lala, P.K.2
  • 4
    • 0028737580 scopus 로고
    • Synthesis of multi-level self-checking logic
    • F. Salice M. G. Sami D. Sciuto Synthesis of multi-level self-checking logic Proc. IEEE DFT'94 115 123 Proc. IEEE DFT'94 Seattle U. S. A. 1994
    • (1994) , pp. 115-123
    • Salice, F.1    Sami, M.G.2    Sciuto, D.3
  • 5
    • 77954564602 scopus 로고    scopus 로고
    • Design of Self-Checking Combinational Circuits with Low Area Overhead
    • V. V. Saposhnikov A. Morosov V. Saposhnikov M. Gossel Design of Self-Checking Combinational Circuits with Low Area Overhead Proc. IEEE Int. On-Line Testing Workshop '96 56 67 Proc. IEEE Int. On-Line Testing Workshop '96 Biarritz France 1996
    • (1996) , pp. 56-67
    • Saposhnikov, V.V.1    Morosov, A.2    Saposhnikov, V.3    Gossel, M.4
  • 7
    • 0028728155 scopus 로고
    • Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection
    • N. A. Touba E. J. McCluskey Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection Proc. of Int. Conf. on Computer-Aided Design (ICCAD) 651 654 Proc. of Int. Conf. on Computer-Aided Design (ICCAD) 1994
    • (1994) , pp. 651-654
    • Touba, N.A.1    McCluskey, E.J.2
  • 10
    • 0030405342 scopus 로고    scopus 로고
    • Redundant Faults in TSC Networks: Definition and Removal
    • C. Bolchini F. Salice D. Sciuto Redundant Faults in TSC Networks: Definition and Removal Proc. IEEE DFT'96 277 285 Proc. IEEE DFT'96 Boston U. S. A. 1996
    • (1996) , pp. 277-285
    • Bolchini, C.1    Salice, F.2    Sciuto, D.3
  • 11
    • 0030685610 scopus 로고    scopus 로고
    • Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks
    • II
    • C. Bolchini F. Salice D. Sciuto Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks Proc. Seventh Great Lakes Symposium on VLSI (GLSVLSI '97) 32 37 Proc. Seventh Great Lakes Symposium on VLSI (GLSVLSI '97) Urbana USA II 1997
    • (1997) , pp. 32-37
    • Bolchini, C.1    Salice, F.2    Sciuto, D.3
  • 12
    • 0030672646 scopus 로고    scopus 로고
    • A Novel Methodology for Designing TSC Combinational Networks based on the Parity Bit Code
    • F
    • C. Bolchini F. E Salice D. Sciuto A Novel Methodology for Designing TSC Combinational Networks based on the Parity Bit Code Proc. ED&TC'97 440 444 Proc. ED&TC'97 Paris F 1997
    • (1997) , pp. 440-444
    • Bolchini, C.1    Salice, F.E2    Sciuto, D.3
  • 14
    • 85176686032 scopus 로고
    • Optimal Negative Unate Synthesis of Network with Inputs and Outputs Encoded with All-Unidirectional-Error-Detecting Codes
    • C. Bolchini Optimal Negative Unate Synthesis of Network with Inputs and Outputs Encoded with All-Unidirectional-Error-Detecting Codes Jan. 1995 Politecnico di Milano, Dip. di Elettronica e Informazione
    • (1995)
    • Bolchini, C.1
  • 15
    • 0025386807 scopus 로고    scopus 로고
    • Multilevel Logic Synthesis
    • R. K. Brayton R. Rudell A. Sangiovanni-Vincentelli Multilevel Logic Synthesis Proceedings of the IEEE 78 2 264 300 Proceedings of the IEEE 90-Feb.
    • , vol.78 , Issue.2 , pp. 264-300
    • Brayton, R.K.1    Rudell, R.2    Sangiovanni-Vincentelli, A.3
  • 16
    • 0003934798 scopus 로고    scopus 로고
    • SIS: A System for Sequential Circuit Synthesis
    • Berkeley
    • SIS: A System for Sequential Circuit Synthesis Berkeley UCB/ERL M92/41 Dept. of Electrical Engineering and Computer Science, University of California


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.