Sensitisable-path-oriented clustered voltage scaling technique for low power

IEE Proceedings: Computers and Digital Techniques

Volumn 145, Issue 4, 1998, Pages 301-307

  Jou, J Y ^a   Chou, D S ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Benchmark circuits; Clustered voltage scaling technique

Indexed keywords

ALGORITHMS; BENCHMARKING; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LOGIC GATES; OPTIMIZATION;

BENCHMARK CIRCUITS; CLUSTERED VOLTAGE SCALING TECHNIQUE; POWER CONSUMPTION;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0032118764     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19982018     Document Type: Article

References (12)

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