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Volumn 12, Issue 2, 1993, Pages 185-195

Critical Path Selection for Performance Optimization

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CRITICAL PATH ANALYSIS; OPTIMIZATION; PERFORMANCE;

EID: 0027541140     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.205000     Document Type: Article
Times cited : (31)

References (18)
  • 2
    • 0025505723 scopus 로고
    • Timing verification using statically sensitizable paths
    • Oct.
    • J. Benkoski et al., “Timing verification using statically sensitizable paths,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 1073–1084, Oct. 1990.
    • (1990) IEEE Trans. Computer-Aided Design , vol.9 , pp. 1073-1084
    • Benkoski, J.1
  • 4
    • 0025537125 scopus 로고
    • Timing Optimization for multi-level combinational networks
    • K. Chen and S. Muroga, “Timing Optimization for multi-level combinational networks,” in Proc. 27th Design Automation Conf., 1990, pp. 339–344.
    • (1990) Proc. 27th Design Automation Conf. , pp. 339-344
    • Chen, K.1    Muroga, S.2
  • 5
    • 0023230725 scopus 로고
    • Transistor sizing in CMOS circuits
    • M. Cirit, “Transistor sizing in CMOS circuits,” in Proc. 24th Design Automation Conf, 1987, pp. 121–124.
    • (1987) Proc. 24th Design Automation Conf. , pp. 121-124
    • Cirit, M.1
  • 6
    • 0021499970 scopus 로고
    • LSS: A system for production logic synthesis
    • J. Darringer et al., “LSS: A system for production logic synthesis,” IBM, Tech. Rep., 1984.
    • (1984) IBM, Tech. Rep.
    • Darringer, J.1
  • 7
    • 0022953026 scopus 로고
    • Performance-oriented synthesis in the Yorktown silicon compiler
    • G. DeMicheli, “Performance-oriented synthesis in the Yorktown silicon compiler,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1986, pp. 138–141.
    • (1986) Proc. IEEE Int. Conf. Computer-Aided Design , pp. 138-141
    • DeMicheli, G.1
  • 9
    • 0025531379 scopus 로고
    • A depth-decreasing heuristic for combinational logic; or How to Convert a ripple-carry adder into a carry-lookahead adder or anything in-between
    • J. Fishburn, “A depth-decreasing heuristic for combinational logic; or How to Convert a ripple-carry adder into a carry-lookahead adder or anything in-between,” in Proc. 27th Design Automation Conf., 1990, pp. 361–364.
    • (1990) Proc. 27th Design Automation Conf. , pp. 361-364
    • Fishburn, J.1
  • 11
  • 13
    • 0022188112 scopus 로고
    • Algorithms for automatic transistor sizing in CMOS digital circuits
    • W. Kao, N. Fathi, and C. Lee, “Algorithms for automatic transistor sizing in CMOS digital circuits,” in Proc. 22nd Design Automation Conf., 1985, pp. 781–784.
    • (1985) Proc. 22nd Design Automation Conf. , pp. 781-784
    • Kao, W.1    Fathi, N.2    Lee, C.3
  • 14
  • 15
    • 0024911062 scopus 로고
    • Transistor size optimization in the tailor layout system
    • D. Maple, “Transistor size optimization in the tailor layout system,” in Proc. 26th Design Automation Conf., 1989, pp. 43–48.
    • (1989) Proc. 26th Design Automation Conf. , pp. 43-48
    • Maple, D.1
  • 16
    • 0024890438 scopus 로고
    • Efficient algorithms for computing the longest viable path in a combinational network
    • P. McGeer and R. Brayton, “Efficient algorithms for computing the longest viable path in a combinational network,” in Proc. 26th Design Automation Conf., 1989, pp. 561–567.
    • (1989) Proc. 26th Design Automation Conf. , pp. 561-567
    • McGeer, P.1    Brayton, R.2
  • 18
    • 0024139932 scopus 로고
    • An electrical optimizer that considers physical layout
    • F. Obermeier and R. Katz, “An electrical optimizer that considers physical layout,” in Proc. 25th Design Automation Conf., 1988, pp. 453–459.
    • (1988) Proc. 25th Design Automation Conf. , pp. 453-459
    • Obermeier, F.1    Katz, R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.