Timing optimization by gate resizing and critical path identification

Proceedings - Design Automation Conference

Volumn , Issue , 1993, Pages 135-139

  Jone, Wen Ben ^a   Fang, Chen Liang ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LOGIC GATES; OPTIMIZATION; PERFORMANCE; TIMING CIRCUITS;

GATE RESIZING; PATH IDENTIFICATION; TIMING OPTIMIZATION;

VLSI CIRCUITS;

EID: 0027277654     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)