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Volumn 41, Issue 4, 1994, Pages 1187-1191

A 64-ch Time Memory Cell Module with a DSP and a VME Interface

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSOR; TIME MEMORY CELL MODULE; VME INTERFACE; WIRE CHAMBER APPLICATIONS;

EID: 0028493961     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.322881     Document Type: Article
Times cited : (6)

References (4)
  • 1
    • 0026837175 scopus 로고
    • A CMOS 4 ch x 1 k Time Memory LSI with 1 ns/bit Resolution
    • Y. Arai and T. Matsumura and K. Endo; “A CMOS 4 ch x 1 k Time Memory LSI with 1 ns/bit Resolution”, IEEE Journal of Solid-State Circuits, Vol.27, No.3, March 1992, p. 359-364.
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , Issue.3 , pp. 359-364
    • Arai, Y.1    Matsumura, T.2    Endo, K.3
  • 3
    • 0026904557 scopus 로고
    • Development of a CMOS Time Memory Cell VLSI and a CAMAC Module with 0.5 ns Resolution
    • Y. Arai, M. Ikeno and T. Matsumura; “Development of a CMOS Time Memory Cell VLSI and a CAMAC Module with 0.5 ns Resolution”, IEEE Trans. on Nucl. Sci. Vol. 39, No. 4 (1992)784-788.
    • (1992) IEEE Trans. on Nucl. Sci , vol.39 , Issue.4 , pp. 784-788
    • Arai, Y.1    Ikeno, M.2    Matsumura, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.