A CMOS Four-Channel × 1K Time Memory LSI with 1-ns/b Resolution

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 3, 1992, Pages 359-364

  Arai, Yasuo ^a   Matsumura, Tsuneo ^b   Endo, Ken Ichi ^b  

^a HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION KEK   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL; INTEGRATED CIRCUITS, CMOS - DESIGN; INTEGRATED CIRCUITS, CMOS - PERFORMANCE; INTEGRATED CIRCUITS, LSI - DESIGN; INTEGRATED CIRCUITS, LSI - PERFORMANCE;

FEEDBACK CIRCUITS; TIME MEMORY CELLS; TIME TO DIGITAL CONVERSION;

DATA CONVERSION, ANALOG TO DIGITAL;

EID: 0026837175     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.121558     Document Type: Article

References (3)

1. Y. Arai and T. Baba, “A CMOS time to digital converter VLSI for high-energy physics,” in 1988 Symp. VLSI Circuits, Dig. Tech. Papers, Aug. 1988, IEEE Cat. no. 88 TH 0227–9, pp. 121–122.
2. A. Stevens et al., “A time-to-voltage converter and analog memory for colliding beam detectors,” IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 748-1752, Dec. 1989.
3. O. Sasaki et al., “1.2 GHz GaAs shift register IC for dead-time-less TDC application,” IEEE Trans. Nucl. Sci., vol. 36, p. 512, 1989.