A new experimental technique to evaluate the plasma induced damage at wafer level testing

Microelectronics Reliability

Volumn 38, Issue 6-8, 1998, Pages 919-924

  Pantisano, L ^a,b   Paccagnella, A ^a,b   Pettarin, L ^a   Scarpa, A ^a   Valentini, G ^c   Baldi, L ^c   Alba, S ^c  

^a UNIVERSITY OF PADOVA   (Italy)

^b INFM   (Italy)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; PASSIVATION; PLASMA APPLICATIONS; SILICON WAFERS; STRESS ANALYSIS;

WAFER LEVEL TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0032084091     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(98)00102-4     Document Type: Article

References (7)

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3. st Symp. Plasma Process-Induced Damage, 1996, 11-14.
4. D.J. DiMaria. J. Appl. Phys. 47(1976), 4073.
5. st Symp. Plasma Process-Induced Damage, 1996, 7-10.
6. st Symp. on plasma Process-Induced Damage, 1996, 43-46.
7. st Symp. Plasma Process-Induced Damage, 1996, 81-83.